zl30406 Zarlink Semiconductor, zl30406 Datasheet - Page 6

• Manufacturer Part Number: zl30406
• Description: Sonet/sdh Clock Multiplier Pll
• Manufacturer: Zarlink Semiconductor

1.4
The output of the VCO is used by the Output Interface Circuit to provide four LVPECL differential clocks at
77.76 MHz, one programmable CML differential clock (19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz) controlled
with FS1-2 pins and a single-ended 19.44 MHz output clock. This block provides also a 19.44 MHz feedback clock
that closes PLL loop. Each output clock can be enabled or disabled individually with the associated Output Enable
pin.
To reduce power consumption and achieve the lowest possible intrinsic jitter the unused output clocks must be
disabled. If any of the LVPECL outputs are disabled they must be left open without any terminations.
The output clock frequency of the OC-CLKo CML differential output clock is selected with FS1-2 pins as shown in
the following table.
Output Interface Circuit
Table 2 - OC-CLKo Clock Frequency Selection
Output Clocks
OC-CLKoP/N
FS2
C77oP/N-A
C77oP/N-B
C77oP/N-C
C77oP/N-D
Table 1 - Output Enable Control
0
0
1
1
C19o
Zarlink Semiconductor Inc.
ZL30406
FS1
0
1
0
1
6
Output Enable Pins
155.52 MHz
Frequency
19.44 MHz
38.88 MHz
77.76 MHz
OC-CLKo
OC-CLKoEN
C77oEN-C
C77oEN-D
C77oEN-A
C77oEN-B
C19oEN
Data Sheet