zl30406 Zarlink Semiconductor, zl30406 Datasheet - Page 11

• Manufacturer Part Number: zl30406
• Description: Sonet/sdh Clock Multiplier Pll
• Manufacturer: Zarlink Semiconductor

2.3
The ZL30406 has four differential 77.76 MHz LVPECL outputs, which can be used to drive four different OC-3/OC-
12/OC-48 devices such as framers, mappers and SERDES. In the case where fewer than four clocks are required,
a user can disable unused LVPECL outputs on the ZL30406 by pulling the corresponding enable pins low. When
disabled, voltage at the both pins of the differential LVPECL output will be pulled up to Vcc - 0.7 V.
For applications requiring the LVPECL outputs to be in a tri-state mode, external AC coupling capacitors can be
used as shown in Figure 10. Typically this might be required in hot swappable applications.
Resistors R1 and R2 are required for DC bias of the LVPECL driver. Capacitors C1 and C2 are used as AC
coupling capacitors. During disable mode (C77oEN pin pulled low) those capacitors present infinite impedance to
the DC signal and to the receiving device this looks like a tristated (High-Z) output. Resistors R3, R4, R5 and R6
are used to terminate the transmission line with 50 ohm impedance and to generate DC bias voltage for the
LVPECL receiver. If the LVPECL receiver has an integrated 50 ohm termination and bias source, resistors R3, R4,
R5 and R6 should not be populated.
Tristating LVPECL Outputs
ZL30406
C77oEN
Figure 10 - Tristatable LVPECL Outputs
R1
200
Zarlink Semiconductor Inc.
R2
200
ZL30406
C2
0.1 u
C1
0.1 u
11
Z=50
Z=50
3.3 V 3.3 V
R3
127
R4
82.5
R6
82.5
R5
127
Data Sheet