zl30105 Zarlink Semiconductor, zl30105 Datasheet - Page 19

• Manufacturer Part Number: zl30105
• Description: Stratum 3 Redundant System Clock Synchronizer For T1/e1/sdh, Advanced Tca And H.110
• Manufacturer: Zarlink Semiconductor

Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and
based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is
dependent on the state of the ZL30105.
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In Holdover Mode, the DCO is free running at a frequency equal to the frequency that the DCO was generating in
Normal Mode. The frequency in Holdover mode is calculated from frequency samples stored 26 ms to 52 ms before
the ZL30105 entered Holdover mode. This ensures that the coarse frequency monitor and the single cycle monitor
have time to disqualify a bad reference before it corrupts the holdover frequency.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source.
Lock Indicator - the lock detector monitors if the output value of the phase detector is within the
phase-lock-window for a certain time. The selected phase-lock-window guarantees the stable operation of the
LOCK pin with maximum network jitter and wander on the reference input. If the DPLL goes into Holdover mode
(auto or manual), the LOCK pin will initially stay high for 1 s in Primary Master mode. In Secondary Master mode,
LOCK remains high for 0.1 s. If at that point the DPLL is still in holdover mode, the LOCK pin will go low;
subsequently the LOCK pin will not return high for at least the full lock-time duration. In Freerun mode the LOCK pin
will go low immediately.
3.5
The output of the DCO is used by the frequency synthesizers to generate the output clocks and frame pulses which
are synchronized to one of three reference inputs (REF0, REF1 or REF2). The frequency synthesizer uses digital
techniques to generate output clocks and advanced noise shaping techniques to minimize the output jitter. The
clock and frame pulse outputs have limited driving capability and should be buffered when driving high capacitance
loads.
3.6
As shown in Figure 1, the state machine controls the TIE Corrector Circuit and the DPLL. The control of the
ZL30105 is based on the inputs MODE_SEL1:0, REF_SEL1:0 and HMS.
3.7
The ZL30105 can use either a clock or crystal as the master timing source. For recommended master timing
circuits, see the Applications - Master Clock section.
Frequency Synthesizers
State Machine
Master Clock
Zarlink Semiconductor Inc.
ZL30105
19
Data Sheet