ml87v2105 Oki Semiconductor, ml87v2105 Datasheet - Page 22

• Manufacturer Part Number: ml87v2105
• Description: Video Signal Noise Reduction Ic With A Built-in 5.6 Mbit Frame Memory
• Manufacturer: Oki Semiconductor

OKI Semiconductor
Input 16-bit mode
The data and control signal interfaces according to input system modes are as follows.
#IICLK
* By setting POFF (SUB:41h-bit[6]) = 1, SAV and EAV parity bits can be invalidated.
CI[7:0]
YI[7:0]
ICLK
Input 16-bit mode
Vertical sync signal:
Horizontal sync signal:
Data input pin:
Input system clock frequency: f
Clip level:
Input 8-bit mode
Vertical sync signal:
Horizontal sync signal:
Data input pin:
Input system clock frequency: f
Clip level:
ITU-R BT.656 mode
Vertical sync signal:
Horizontal sync signal:
Data input pin:
Input system clock frequency: f
Clip level:
# : Internal signal
Yn
Cn
Yn+1
Cn+1
Figure F1-2-1 (1) Input Data Timing
Cn+2
Yn+2
IVS
IHS
YI[7:0], CI[7:0] (YCbCr-4:2:2)
None
IVS
IHS
YI[7:0], (YCbCr-4:2:2)
None
SAV, EAV split
SAV, EAV split
YI[7:0] (YCbCr-4:2:2)
00h
ICLK
ICLK
ICLK
Yn+3
Cn+3
= 13.5/16/18 MHz
= 27/32/36 MHz
= 27/32/36 MHz2
01h, FFh
FEh
Input 8-bit mode, ITU-R BT.656 mode
#IICLK
CI[7:0]
YI[7:0]
ICLK
Cbn
don’t care (non-connect)
Yn
PEDL87V2105-02
Crn
ML87V2105
Yn+1
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