ml87v2105 Oki Semiconductor, ml87v2105 Datasheet
ml87v2105
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ml87v2105 Summary of contents
Page 1
... The ML87V2105 also features an automatic noise reduction mode that automatically detects the noise level in the input video data to set the optimum noise reduction. Because it is possible to select the same format for output as for input, the ML87V2105 can be introduced into an existing system, making it easy to achieve noise reduction. ...
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... OKI Semiconductor BLOCK DIAGRAM YI0-7 x16 CI0-7 ICLK IVS IHS SCL SDA SLA1 SLA2 Register MODE0-2 TEST1-7 RESET Frame Memory Input/Output 5.6Mbits Process Block + 3D NR Memory Controller 2 I C-bus Control I/F Signal PEDL87V2105-02 ML87V2105 x16 YO0-7 CO0-7 OVS OHS HREF CLKO 2/103 ...
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... N.C. 82 N.C. 83 N.C. 84 N.C. 85 N.C. 86 TEST5 TEST4 89 TEST3 90 TEST2 91 TEST1 92 N.C. 93 N.C. 94 N.C. 95 TESTM 96 SELF N. 100 DD ML87V2105TB (TQFP100-P-1414-0.50-K) PEDL87V2105-02 ML87V2105 N. HREF 47 OVS 46 OHS 45 N.C. 44 N. N.C. N. CLKO 35 MODE2 34 N.C. 33 MODE1 32 ...
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... Power supply 3.3 V Input system clock pin Ground Power supply 3.3 V Unused pin Ground Input system vertical sync signal input pin Input system horizontal sync signal input pin Unused pin 2 C-bus control possible) Power supply 3.3 V Ground Unused pin Unused pin PEDL87V2105-02 ML87V2105 4/103 ...
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... Luminance signal output pin – bit 5 Luminance signal output pin – bit 6 Luminance signal output pin – bit 7 (MSB) Ground Test input pin – bit 7 (1: test mode) Test input pin – bit 6 (1: test mode) System reset/input pin 0: System reset 1: Operation PEDL87V2105-02 ML87V2105 5/103 ...
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... Unused pin Ground Unused pin Unused pin Unused pin Unused pin Unused pin Unused pin Unused pin Unused pin Power supply 3.3 V Unused pin Unused pin Unused pin Self refresh setting pin (0: Self refresh stopped, 1: Self refresh operated) Ground PEDL87V2105-02 ML87V2105 6/103 ...
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... Typ. V 3.0 3 — Symbol Min. C — — io1 C — io2 C — o PEDL87V2105-02 ML87V2105 Rating Unit –0 4.6 V +0.5≦4 – 150 C Max. Unit 3 3 MHz Max. Unit 5 pF ...
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... DIDO 0 reaches 3.0 V after the power is turned on, and when DD reaches 3.0 V after the power is turned on, and DD PEDL87V2105-02 ML87V2105 ( Min. Max. Unit V x 0 – ...
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... ICLK input/output timing ICLK DATA & CONTROL INPUT(ICLK) DATA & CONTROL OUTPUT(ICLK) CLKO (CKINV=0) CLKO (CKINV=1) 2. Data through mode input/output timing DATA & CONTROL INPUT DATA & CONTROL OUTPUT t ICLK t t IIH IISU t IOD t CKD t CKD t DIDO PEDL87V2105-02 ML87V2105 50% 50% 50% 50% 50% 50% 50% 9/103 ...
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... FUNCTIONAL DESCRIPTION 1 Signal Processing The ML87V2105 generates memory control signals from the input vertical and horizontal sync signals (IVS and IHS or SAV and EAV), reads and writes the frame memory data, and performs noise reduction processing on input and memory data to achieve 3D noise reduction. ...
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... A input, the pulse toggled by IVS is regarded as the field pulse. IVS IHS 0.5H pulse #IF Figure F1-1-2 (1) Input System Field A Detection Timing IVS IHS 0.5H pulse #IF Figure F1-1-2 (2) Input System Field B Detection Timing PEDL87V2105-02 ML87V2105 Field A detection phase Field A detection phase Field B detection phase Field B detection phase 11/103 ...
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... Figure F1-1-2 (3) Field Detection during Continuous Same Field Input (FCON = 1) IHS or 0.5H pulse Field judgement margin (10 clocks) Field judgement uncertainty area Figure F1-1-2 (4) Field Judgment Uncertainty Area Field A Field B Field A judgment area Field judgement margin (10 clocks) Field judgement uncertainty area PEDL87V2105-02 ML87V2105 Field A Field A Field B judgment area 12/103 ...
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... Figure F1-1-3(2) Input Horizontal Valid Pixels HMD[1:0] Valid lines 0h 288 0h 243 1h 288 1h 243 2h 288 2h 243 Other Cannot be set in test mode. 243/288 lines : Valid data : Invalid data 720/640/768 pixels : Valid data : Invalid data PEDL87V2105-02 ML87V2105 Valid pixels 720 720 768 640 768 768 13/103 ...
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... Figure F1-1-3 (3) Input System Vertical Valid Line Start Timing IVPS position (number of IHS’s from IVR) NPVWE = 8h 20 (default) 7 (–7 lines) 14 (default) 24 (default (default) * Test modes (Not settable) 7 lines 7 lines IVPS #: Internal signal PEDL87V2105-02 ML87V2105 NPVWE = Fh 27 (+7 lines) 21 (+7 lines) 31 (+7 lines (+7 lines) * 288/243 lines 14/103 ...
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... Test modes (Not settable) 127pixels IHPS 640/720 /768ixels 1pixel Valid data PEDL87V2105-02 ML87V2105 NHPWE = FFh 271 (+127 pixels) 265 (+127 pixels) 303 (+127 pixels) 267 (+127 pixels) 303 (+127 pixels) 269 (+127 pixels) 1pixel 15/103 ...
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... Recommended input IVS polarity IVSINV = 1 IVS IWE Value set by NPVWE[3:0] 2 C-bus setting register IHSINV (SUB:42h-bit[1]). Table F1-1-4 (2) IHSINV Setting IHSINV Input IHS polarity Positive (default) Negative IHSINV = 1 IHS IWE PEDL87V2105-02 ML87V2105 IVR generation edge Rising edge Falling edge Value set by NPVWE[3:0] Value set by NPHWE[7:0] 16/103 ...
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... Field Internal IVEM decision field setting PEDL87V2105-02 ML87V2105 2 C-bus Field Field after Valid data start compensation position n No compensation compensation 17/103 ...
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... Field A input IHS IVS n-1 n #IVR #IF Field B input IHS IVS n-1 n #IVR #IF Input sync signal phase 4 Field A input IHS IVS n #IVR #IF Field B input IHS IVS n-1 n n+1 0 #IVR #IF PEDL87V2105-02 ML87V2105 n-1 n n+1 18/103 ...
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... Stopped (field A maintained, still image output) Stopped (field B maintained, still image output) Stopped (either field output maintained, still image output) Rostore write setting PEDL87V2105-02 ML87V2105 19/103 ...
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... The data output from the memory is in 4:1:1 format converted to 4:2:2 format by interpolating linearly color difference data. Therefore, the color difference data has a lower band than normal data. Output Still Image Mode [0] X Field still image 0 Frame still image 1 Frame median still image Valid data (4:2:2) Valid data (4:1:1) Valid data (4:1:1) PEDL87V2105-02 ML87V2105 20/103 ...
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... Cr03 — — Cr02 — — Cr01 — — Cr00 — — PEDL87V2105-02 ML87V2105 2 C-bus setting register IRMON Mode Input 16-bit mode Input 8-bit mode Cr07 Y17 Cr06 Y16 Cr05 Y15 Cr04 Y14 Cr03 Y13 Cr02 Y12 Cr01 ...
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... Input 8-bit mode, ITU-R BT.656 mode ICLK #IICLK Yn+2 Yn+3 YI[7:0] CI[7:0] Cn+2 Cn+3 Figure F1-2-1 (1) Input Data Timing IVS IHS YI[7:0], CI[7:0] (YCbCr-4:2:2) = 13.5/16/18 MHz ICLK None IVS IHS YI[7:0], (YCbCr-4:2:2) = 27/32/36 MHz ICLK None SAV, EAV split SAV, EAV split YI[7:0] (YCbCr-4:2:2) = 27/32/36 MHz2 ICLK 00h 01h, FFh FEh PEDL87V2105-02 ML87V2105 Cbn Yn Crn Yn+1 don’t care (non-connect) 22/103 ...
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... Positive polarity IHS rise (horizontal sync front edge) Positive polarity IHS fall (horizontal sync rear edge) Negative polarity IHS fall (horizontal sync front edge) Negative polarity IHS rise (horizontal sync rear edge) Usage conditions (8-bit 4:2:2 mode) Crn PEDL87V2105-02 ML87V2105 Yn Cbn Yn+1 23/103 ...
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... Cr00 — — Input Output 16 bits+Sync(H,V) 16 bits + Sync(H,V) 8 bits+Sync(H,V) 8 bits + Sync(H,V) 8 bits+Sync(H,V) 8 bits + Sync(H,V) ITU-R BT.656 16 bits + Sync(H,V) ITU-R BT.656 ITU-R BT.656 + Sync(H,V) PEDL87V2105-02 ML87V2105 Cb07 Y17 Cb06 Y16 Cb05 Y15 Cb04 Y14 Cb03 Y13 Cb02 Y12 Cb01 Y11 Cb00 Y10 — ...
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... SAV Cb0 Y0 Cr0 Y1 [DOSEL=0] YO[7:0] CO[7:0] [DOSEL=1] YO[7:0] Figure F1-2-2(3) I/O Delay in the ITU-R BT.656 Mode Y0 Y1 Cb0 Cr0 23(ICLK) Cb0 Y0 Cr0 Y1 46(ICLK) 48(ICLK) 46(ICLK 48(ICLK) FF PEDL87V2105-02 ML87V2105 Cb0 Cr0 Cb1 Cb0 Cr0 Cb0 Cb0 Y0 Cr0 Y1 SAV Cb0 Cr0 Cb0 ...
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... MSB Motion detection Chrominance noise detection Color difference Non- Limiter motion level linear filter compen- sation Motion detection Noise detection + motion compensation PEDL87V2105-02 ML87V2105 + Luminance - output data - Field memory NR recursive data Color + - difference output data - Luminance interlock motion Field compensation memory NR recursive data – ...
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... Figure F1-3 (3) Noise Reduction Correlative Relationships Frame NR There is motion between the frames Figure F1-3 (4) Adaptive Noise Reduction Principles Time axis 2V Direction target pixel : NR There is an edge between the lines. Field NR x2 There is motion between the fields PEDL87V2105-02 ML87V2105 1H Line NR 27/103 ...
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... NR (uses frames and fields) 2D adaptive frame-recursive NR (uses frames and lines) Frame-recursive NR 2D adaptive field-recursive NR (uses fields and lines) Field-recursive NR margin No Yes Frame NR performance emphasized (greater NR, increased afterimage) No Yes Frame NR performance emphasized (greater NR, increased afterimage) PEDL87V2105-02 ML87V2105 Remarks Remarks 28/103 ...
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... CNS[5:0] -1/2 -3/2 Input noise detection line inclination 1 or 7/8 or 3/4 or 1/2 Non-noise detection area Noise convergence line inclination -1 or -3/4 or -1/2 or -3/2 Noise detection area PEDL87V2105-02 ML87V2105 YNS[5:0](SUB:4Ch-bit[5:0]), Noise upper limit line Offset Inclination Offset YLM[4:0] 0 CLM[4:0] Noise detection line Noise upper limit Noise upper limit line ...
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... Table F1-3-3 (2) Luminance 3 Continuous Code Motion Detection Motion detection condition - (1/8)z + (1/2)z + (1/8)z + (1/8)z Motion Flag (YMT) | LY| > LY| > YNS[5:0] | LY| YNS[5:0] Motion flag (YMT3) | LY| > LY| YMS[3:0] | LY| < YMS[3:0] PEDL87V2105-02 ML87V2105 30/103 ...
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... This motion flag is used in adjacent pixel motion compensation. Table F1-3-3 (5) Color Difference Level Motion Detection Motion detection condition Motion flag (YMT4) | LY| > LY| YMS[3:1] | LY| < YMS[3:1] Motion flag (YMT5) | LY| > LY| YMS[3:2] | LY| < YMS[3: (1/2)z + (1/4)z Motion flag (CMT) | LC| > LC| > CNS[5:0] | LC| CNS[5:0] PEDL87V2105-02 ML87V2105 31/103 ...
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... Luminance 5 continuous codes color difference motion compensation Motion compensation Remarks mode None Detected noise as is (Detected noise) x Normal reduction (Reduction coefficient) (Detected noise) x Absolute noise reduction (Reduction coefficient) Noise 0 judgment Noise 0 (NROFF) PEDL87V2105-02 ML87V2105 for the noise detected in Section 1.3.2 Remarks 32/103 ...
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... PEDL87V2105-02 ML87V2105 YABN = 1 1 3/4 3/4 5/8 5/8 9/16 9/16 17/32 Remarks (Detected noise) x (Detected noise) x Noise 0 judgment (NROFF) CABN=1 1 3/4 3/4 5/8 3/4 5/8 5/8 9/16 5/8 9/16 9/16 17/32 9/16 17/32 17/32 1/2 33/103 ...
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... C-bus interface. Table F1-3-6 NRDEMO Setting Left side of screen [ setting value X Stop NR X Stop Setting value 1 NR Setting value PEDL87V2105-02 ML87V2105 2 C-bus interface. Right side of screen NR setting value Stop NR NR setting value Adaptive NR Adaptive 2DNR Right side area of screen 34/103 ...
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... Internal signal Figure F1-3-7 (1) Vertical Blanking Noise Status Detection timing (NDTC = 0) #Valid data signal IHS NRDTP[3:0] (DTPSL=0) NRDTP[3:0] (DTPSL=1) #: Internal signal Figure F1-3-7 (2) Vertical Blanking Noise Status Detection timing (NDTC = NDTP[3:0]+1 NDTP[3:0]+1 PEDL87V2105-02 ML87V2105 35/103 ...
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... NRDTF Noise detection field 0 Field A 1 Field B Noise detection line 1 line set at the NRDTP[3:0] position YNAMS Noise detection value CNAMS 0 8-frames average 1 Single frame Noise detection area Vertical blanking period Vertical blanking period + valid data period PEDL87V2105-02 ML87V2105 Field A Field B 36/103 ...
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... CBAVRO[6:0] > CAVR1[5:0] x (hysteresis coefficient) YAH1 Noise reduction direction CAH1 switching coefficient 0 3/4 1 7/8 Noise reduction direction judging threshold value Noise increase direction judging threshold value 0 YAVR1[6:0] CAVR1[6:0] PEDL87V2105-02 ML87V2105 After transition YBDTO After transition CBDTO Basic average noise value ...
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... Valid data period noise level level Color difference judgment — Blanking period noise level — Valid data period noise level Blanking period noise level Valid data period noise level Valid data period noise level level PEDL87V2105-02 ML87V2105 level noise level 38/103 ...
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... Condition YAVRO[6:0] YAVR2[6:0] YAVRO[6:0] > YAVR2[6:0] YAVRO[6:0] YAVR2[6:0] x (hysteresis coefficient) YAVRO[6:0] > YAVR2[6:0] x (hysteresis coefficient) Condition CAVRO[6:0] CAVR2[6:0] CAVRO[6:0] > CAVR2[6:0] CAVRO[6:0] CAVR2[6:0] x (hysteresis coefficient) CAVRO[6:0] > CAVR2[6:0] x (hysteresis coefficient) PEDL87V2105-02 ML87V2105 After transition YDTO1 After transition CDTO1 After transition YDTO2 0 ...
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... Noise reduction direction judging threshold value 1 Noise increase direction judging threshold value 1 Noise reduction direction judging threshold value 2 Noise increase direction judging threshold value 2 Set by YAH2, CAH2 YAVR1[6:0] YAVR2[6:0] CAVR1[6:0] CAVR2[6:0] PEDL87V2105-02 ML87V2105 Average noise value YAVRO[6:0] CAVRO[6:0] 40/103 ...
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... Color difference judgment maximum noise value Color difference judgment noise status 2 (noise medium/high judgment) Luminance blanking average noise value Luminance blanking noise status (basic noise judgment) Color difference blanking average noise value Color difference blanking noise status (basic noise judgment) PEDL87V2105-02 ML87V2105 41/103 ...
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... AMM (SUB:49h-bit[3]) and overall follow-up mode by YANRM (SUB:4Ah-bit[1]), CANRM (SUB:4Bh-bit[1]) can be selected. The noise reduction setting value in auto mode can be precisely set by AYABN (SUB:4Ah-bit[3]), ACABN (SUB:4Bh-bit[3]), AYNS[1:0] (SUB:4Eh-bit[7:6]), ACLM[1:0] (SUB:4Fh-bit[7:6]), AYMS [1:0] (SUB:50h-bit[7:6]), and AYMOFF[3:1] (SUB:51h-bit[7:5]). (SUB:4Ch-bit[7:6]), ACNS[1:0] PEDL87V2105-02 ML87V2105 (SUB:4Dh-bit[7:6]), AYLM [1:0] 42/103 ...
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... Valid data period Fixed value noise follow-up noise reduction noise reduction (with lower limit) PEDL87V2105-02 ML87V2105 Remarks Same as NROFF = 1 AYNS [1:0], YCNA [1:0], AYLM [1:0], YCLM [1:0], and AYMS [1:0] are valid. YNRM, CNRM, YABN and CABN settings are ignored; operation is equivalent to YNRM = 1, CNRM = 1, YABN = 0 and CABN = 0 ...
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... Valid data period Fixed value noise follow-up noise reduction noise reduction (with lower limit) PEDL87V2105-02 ML87V2105 Remarks AYNS [1:0], YCNA [1:0], AYLM [1:0], YCLM [1:0], and AYMS [1:0] are valid. YNRM, CNRM, YABN and CABN settings are ignored; operation is equivalent to YNRM = 1, CNRM = 1, YABN = 0 and CABN = 0. ...
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... Absolute noise reduction mode (equivalent to 1 CABN = 1 operation) AYNS Luminance noise convergence level [1] [ YNS[5:0] + YMAXO[4:0](max:3Fh Smaller of YMAXO[4:0] x 3(max:3Fh) and YNS[5: YNS[5:0] + YMAXO[4:0](max:3Fh Larger of YMAXO[4:0] x 3(max:3Fh) and YNS[5:0] PEDL87V2105-02 ML87V2105 YNS[5:0] YNS[5:0] YNS[5:0] 45/103 ...
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... Color Difference noise upper limit level [1] [ Smaller of CMAXO[4:0] x 0.75 (max:1Fh) and CLM[4: Smaller of CMAXO[4:0](max:1Fh) and CLM[4: Larger of CMAXO[4:0] x 0.75(max:1Fh) and CLM[4: Larger of CMAXO[4:0](max:1Fh) and CLM[4:0] PEDL87V2105-02 ML87V2105 CNS[5:0] CNS[5:0] CNS[5:0] YLM[4:0] YLM[4:0] YLM[4:0] CLM[4:0] CLM[4:0] CLM[4:0] 46/103 ...
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... Smaller of YMAXO[4:0](max:1Fh) and YMS[3:0] YMS[4:0] Luminance motion compensation Motion compensation YMOFF[a] X dependent Motion compensation YMOFF[a] 0 dependent Motion compensation stopped (equivalent 1 to YMOFF[ Luminance motion compensation Motion compensation YMOFF[a] X dependent Motion compensation YMOFF[a] 0 dependent Motion compensation stopped (equivalent 1 to YMOFF[ PEDL87V2105-02 ML87V2105 47/103 ...
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... Luminance adaptive margin setting YFAM dependent Equivalent to YFAM = 1 operation Color Difference adaptive margin setting CFAM dependent Equivalent to CFAM = 1 operation PEDL87V2105-02 ML87V2105 Remarks Equivalent to YMOFF[3: AYABN, ACABN, AYNS[1:0], YCNS[1:0], AYLM[1:0], YCLM[1:0], and AYMS[1:0] are effective. 1/4 of the NR parameter fixed value is the maximum ...
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... When A2OFF = 1 is set, the noise status of the blanking period is the noise follow-up level and where YDTO1 or CDTO1 is 1, the adaptive 2DNR is set to be OFF. Table F1-3-8 (15) Adaptive 2DOFF Settings Blanking period noise YDTO1 or Adaptive 2DNR setting CDTO1 X NR2OFF dependent 0 NR2OFF dependent 1 Adaptive 2DNROFF PEDL87V2105-02 ML87V2105 49/103 ...
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... Noise state detection is not performed at all times if the hysteresis characteristic of noise state detection is not valid (frequent occurrence of state switching). The noise detection is performed by NRDTON = 1 (8 frames or more) at the time of RF channels or input source switching only. Thereafter, settings to hold the noise state etc., at NRDTON = the next switching become necessary. PEDL87V2105-02 ML87V2105 50/103 ...
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... Color difference select signal Output system filed pulse signal 4 l-1 l l+1 l+2 l+3 3 pixels Y_BLK (00, 01, 08, 10 C_BLK (80) Cb0 Cr0 Cb1 Cr1 Horizontal valid data period PEDL87V2105-02 ML87V2105 m pixels Y_BLK (00,01,08,10) Y3 Ym-3 Ym-2 Ym-1 Ym C_BLK (80) Cbn-1 Crn-1 Cbn Crn BLK 51/103 ...
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... OVS output 0 Same polarity as input 1 Reverse polarity of input Table F2-2 (2) OVS Pin Polarity OHSINV OHS output 0 Same polarity as input 1 Reverse polarity of input Table F2-2 (3) HREF Pin Polarity HREF output 0 Same polarity as internally generated 1 Reverse polarity of internally generated PEDL87V2105-02 ML87V2105 Blanking Period 2 C-bus 52/103 ...
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... CLKO [CKINV=1] CLKO Figure F2-4 (1) CLKO Output Timing (16-bit mode) R601 Output signal level range 0 00h to FFh 1 01h to FEh Table F2-4 CLKO Output CKSL CKINV CLKO output X X Hi-Z(Pulldown50k ) 0 0 IICLK 0 1 IICLK inversion 1 0 ICLK 1 1 ICLK inversion t CKD PEDL87V2105-02 ML87V2105 53/103 ...
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... OKI Semiconductor ICLK #IICLK [CKSL=0,CKINV=0] CLKO [CKSL=0,CKINV=1] CLKO [CKSL=1,CKINV=0] CLKO [CKSL=1,CKINV=1] CLKO Figure F2-4 (2) CLKO Output Timing (Input 8-bit/ ITU-R BT.656 mode) PEDL87V2105-02 t CKD ML87V2105 54/103 ...
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... Hi-Z state. Note that CO[7:0] and CLKO pins are internally pulled down with Table F2-5 Input Through Mode Input pin Output pin YI[7:0] YO[7:0] CI[7:0] CO[7:0] IVS OVS OHS IHS HREF Internal Circuit PASS = 0: Internal processing signal output PASS = 1: Signal through PASS Figure F2-5 Input Through Mode PEDL87V2105-02 ML87V2105 Y YO[7:0] CO[7: OVS Y OHS HREF Y 55/103 ...
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... C-bus interface standards of Philips. This allows setting a Table F3 (1) Slave Address Slave Address (Write) Slave Address (Read) 0 B8h 1 BAh 0 BCh 1 BEh A(s) Data 0 A(s) Data n A(s) Data 0 A(s) P A(s) Sr Slave Address R A(s) A(s) Sr Slave Address R A(s) PEDL87V2105-02 ML87V2105 B9h BBh BDh BFh (m) Data 0 A(m) Data (m) Data 0 P 56/103 ...
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... If the setting is performed at a position that contains the above timing, the setting may not finish inside the same field. 2 C-bus Format Description 3-6 ACK Change of Data Allowed 2 C-bus Interface Basic Timing PEDL87V2105-02 ML87V2105 2 9 3-8 P ACK Stop Condition 57/103 ...
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... Regarding the read-only sub-addresses, acknowledge is returned but data write is not performed. Settings such as mode setting, noise reduction function, memory control function, sync signals generation become possible by accessing these registers. All writable registers become readable also. Note: Blank (reserved) registers must be set to 0. PEDL87V2105-02 ML87V2105 58/103 ...
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... ICINV — — — IVEM IFLS IFINV STLM — NPVWE — — NPHWE PEDL87V2105-02 ML87V2105 Initial Sync value BIT1 BIT0 VMD 00h IVS 1 0 R656 DISEL 00h — IHSINV IVSINV 00h IVS STL 00h IVS 1 0 08h ...
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... CAVRO YMAXO — CMAXO — YBAVRO CBAVRO PEDL87V2105-02 ML87V2105 Initial Sync value BIT1 BIT0 NROFF 01h IVS 0 NRDTON NRAUTO 00h IVS YFAM YNRM 10h IVS CFAM CNRM 10h IVS 18h IVS 1 0 0Fh ...
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... RYLM RCLM RNR2 RYMS OFF — — — — SHSDL PEDL87V2105-02 ML87V2105 Initial Sync value BIT1 BIT0 DOSEL — 00h — 00h — Initial Sync value BIT1 BIT0 00h — 00h — OUTDS ...
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... Vertical line operation mode setting [0] 0 625-line mode 1 525-line mode 0 (Not settable) 1 720-pixel mode Square (768/640) pixel mode 768-pixel mode Test mode PEDL87V2105-02 ML87V2105 BIT2 BIT1 BIT0 HMD VMD Sampling frequency 13.5 MHz 14.75/12.272727 MHz 14.75/14.31818 MHz — 62/103 ...
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... Sets external pin/internal registers switching for memory control mode setting Table R2-1 (4) External Pin Setting Switching Setting IRMON 0 1 Input signal level range 00h to FFh ITU-R BT.601 (01h to FEh) Register set mode setting External pin (MODE[2:0]) Internal registers (VMD[0], HMD[0], DISEL) PEDL87V2105-02 ML87V2105 63/103 ...
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... IRMON MODE2 BIT6 BIT5 BIT4 BIT3 POFF IHES ICINV (Reserved) (Reserved) DISEL R656 ITU-R BT.656 mode PEDL87V2105-02 ML87V2105 BIT2 BIT1 BIT0 R656 DISEL Input data format 16-bit 4:2:2 YCbCr 8-bit 4:2:2 YCbCr 64/103 ...
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... POFF Initial value: 0; Setting range Sets ITU-R BT.656 mode parity check. Table R2-2-1 (4) ITU-R BT.656 Mode Parity Check Setting ICINV IICLK polarity 0 At IHS rise reset IHS rise reset: 0 IHES IHS edge for H reset 0 Rise 1 Fall POFF Parity check OFF PEDL87V2105-02 ML87V2105 65/103 ...
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... IHS input polarity 1 Negative polarity (Rise) Positive polarity (Fall) IFINV Detection field pulse 0 Decision result 1 Decision result inversion IFLS Detection field pulse 0 IHS decision 1 0.5H pulse decision PEDL87V2105-02 ML87V2105 BIT2 BIT1 BIT0 IFINV IHSINV IVSINV IVS input polarity 2 IHS input polarity 2 66/103 ...
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... Sets successive same field input countermeasure. Automatically generates both fields by detecting 8 or more successive same fields. Table R2-2-2 (6) Detection Field Pulse Polarity Setting FCON 0 1 IVS reset compensation No compensation Detection field pulse Decision result mode Automatic field generation mode PEDL87V2105-02 ML87V2105 67/103 ...
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... Stop (arbitrary field data hold) Output mode [0] 0 Field output mode 1 Frame output mode (normal) 1 Frame output mode (median) BIT6 BIT5 BIT4 BIT6 BIT5 BIT4 NPHWE PEDL87V2105-02 ML87V2105 BIT3 BIT2 BIT1 BIT0 STL BIT3 BIT2 BIT1 BIT0 NPVWE BIT3 BIT2 ...
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... OKI Semiconductor NPHWE[7:0] Initial value: 1000_0000; Setting range: 0000_0001 to 1111_1111 When IHSINV = 0, sets the number of pixels from the IHS rise position up to the horizontal standard write start position. When IHSINV = 1, sets the number of pixels from the IHS fall position. PEDL87V2105-02 ML87V2105 69/103 ...
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... NR2OFF Left side screen [ setting value X Stop NR. X Stop NR setting value 1 NR setting value PEDL87V2105-02 ML87V2105 BIT2 BIT1 BIT0 NRDEMO NROFF 1 0 Right side screen NR setting value Stop NR. NR setting value Adaptive NR forced ON Adaptive 2DNR forced ON Right side ...
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... Table R2-3-1 (2) 2D Noise Reduction Settings NR2OFF FNRM[1:0] Initial value:0; Setting range Sets the noise reduction recursive mode. Table R2-3-1 (3) Recursive Mode Settings FNRM [1] [ noise reduction 0 ON (adaptive) 1 OFF Mode Frame / field adaptive mode Frame mode Field mode PEDL87V2105-02 ML87V2105 71/103 ...
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... BIT4 BIT3 NDTC NRDTF (Reserved) AMM Noise reduction mode Register fixed mode Auto mode Noise detection Stop (Hold) Updated every frame Color difference noise detection flag mode Color difference independent Luminance linked PEDL87V2105-02 ML87V2105 BIT2 BIT1 BIT0 ACY NRDTON NRAUTO 72/103 ...
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... Basic noise detection period 1 line set by NRDTP[3:0] Multiple lines set by NRDTP[3:0] Noise detection period Vertical blanking area only Vertical blanking area + valid data area PEDL87V2105-02 ML87V2105 YDTO1 = 1, YDTO2 = 1 CDTO1 = 1, CDTO2 = 1 Noise follow-up state (With automatic motion compensation OFF) Noise follow-up state ...
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... CSLT[3:0] Initial value: 0001; Setting range: Refer to Table 2-3-3 (10). Sets color difference noise reduction noise detection line/convergence line inclination. BIT5 BIT4 BIT3 YSLT AYABN BIT5 BIT4 BIT3 CSLT ACABN PEDL87V2105-02 ML87V2105 BIT2 BIT1 BIT0 YABN YFAM YNRM BIT2 BIT1 BIT0 CABN CFAM CNRM 74/103 ...
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... Noise follow-up state luminance mode Normal noise mode Absolute noise mode NRAUTO=1) Noise follow-up state color difference mode Normal noise mode Absolute noise mode PEDL87V2105-02 ML87V2105 75/103 ...
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... X – Setting Noise detection line Noise convergence line coefficient (Inclination) [ 7/8 0 3/4 1 1/2 X – X – X – X – PEDL87V2105-02 ML87V2105 coefficient (Inclination) – – – – 1 (–1) 3/4 (–3/4) 1/2 (–1/2) 3/2 (–3/2) coefficient (Inclination) – – – – 1 (–1) 3/4 (–3/4) 1/2 (–1/2) 3/2 (–3/2) 76/103 ...
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... Figure R2-3-4 Example of Noise Detection by the YNS and CNS Settings BIT6 BIT5 BIT4 BIT3 BIT6 BIT5 BIT4 BIT3 Non-noise detection region Noise detection region YNS[5:0],CNS[5:0]= PEDL87V2105-02 ML87V2105 BIT2 BIT1 BIT0 YNS BIT2 BIT1 BIT0 CNS (Difference between the fields) Input 63 (MAX) 77/103 ...
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... Table R2-3-4 (2) Auto Mode Color Difference Noise Convergence Level Setting (Valid at NRAUTO=1) ACNS [1] [ Noise Follow-up State Noise Convergence Level YNS[5:0] YNS[5:0] + YMAXO[5:0] (Max.: 3Fh) YMAXO[5:0] 3 (Max.: 3Fh) Noise Follow-up State Noise Convergence Level CNS[5:0] CNS[5:9] + CMAXO[5:0] (Max.: 3Fh) CMAXO[5:0] 3 (Max.: 3Fh) PEDL87V2105-02 ML87V2105 78/103 ...
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... Sets auto mode color difference noise upper limit level. Becomes valid in the auto mode noise follow-up state. BIT6 BIT5 BIT4 BIT3 AYNDL BIT6 BIT5 BIT4 BIT3 ACNDL PEDL87V2105-02 ML87V2105 BIT2 BIT1 BIT0 YLM BIT2 BIT1 BIT0 CLM 79/103 ...
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... Non-noise detection region Noise detection region Noise Follow-up State Luminance Noise Upper Limit Level YLM[4:0] YMAXO[4:0] 0.75 (Max.: 1Fh) YMAXO[4:0] (Max.: 1Fh) CLM[4:0] CMAXO[4:0] 0.75 (Max.: 1Fh) CMAXO[4:0] (Max.: 1Fh) PEDL87V2105-02 ML87V2105 YLM[4:0], CLM[4: (Detected noise A) Input 80/103 ...
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... Small (No compensation) Motion decision Large (Compensation operation) Large (Compensation operation) Small (No compensation) Motion decision Large (Compensation operation) Large (Compensation operation) Small (No compensation) Noise follow-up state motion compensation level YMS[3:0] YMAXO[4:0]/2 (Max.: Fh) YMAXO[4:0] (Max.: Fh) PEDL87V2105-02 ML87V2105 BIT2 BIT1 BIT0 YMS 81/103 ...
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... Sets the auto mode 2D noise reduction OFF. If there is a lot of noise in the auto mode, the adaptive 2D noise reduction is turned OFF. Table R2-3-6 (5) Auto Mode 2D Noise Reduction OFF Setting A2OFF noise reduction Depends on NR2OFF setting Adaptive 2DNR OFF in noise status 2 PEDL87V2105-02 ML87V2105 82/103 ...
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... BIT5 BIT4 BIT3 (Reserved BIT5 BIT4 BIT3 4 Luminance motion level detection noise motion compensation Noise follow-up state motion compensation Motion compensation ON Motion compensation OFF PEDL87V2105-02 ML87V2105 BIT2 BIT1 BIT0 YMOFF BIT2 BIT1 BIT0 CMOFF 83/103 ...
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... Luminance horizontal contiguous 4-continuous code motion compensation - ON Luminance horizontal contiguous 4-continuous code motion compensation - OFF Luminance horizontal contiguous 5-continuous code motion compensation - OFF Luminance horizontal contiguous 5-continuous code motion compensation - ON Luminance horizontal contiguous 5-continuous code motion compensation - OFF PEDL87V2105-02 ML87V2105 84/103 ...
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... BIT6 BIT5 BIT4 BIT3 BIT6 BIT5 BIT4 BIT3 YAVR2 BIT6 BIT5 BIT4 BIT3 CAVR2 PEDL87V2105-02 ML87V2105 BIT2 BIT1 BIT0 YAVR1 BIT2 BIT1 BIT0 CAVR1 BIT2 BIT1 BIT0 BIT2 BIT1 BIT0 85/103 ...
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... Coefficient) Level condition (CAVR1[5:0] Coefficient) Level condition (YAVR2[6:0] Coefficient) Level condition (CAVR2[6:0] Coefficient) Noise decrease direction switching coefficient 3/4 7/8 Noise decrease direction switching coefficient 3/4 7/8 PEDL87V2105-02 ML87V2105 State YDTO1 = 0 1 YDTO1 = 1 0 State CDTO1 = 0 1 CDTO1 = 1 0 State YDTO2 = 0 1 YDTO2 = 1 0 State ...
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... Noise decrease direction switching coefficient 3/4 7/8 Noise decrease direction decision threshold value 1 Noise increase direction decision threshold value 1 Noise decrease direction decision threshold value 2 Noise increase direction decision threshold value 2 Set by YAH2, CAH2. YAVR1[6:0] YAVR2[6:0] CAVR1[6:0] CAVR2[6:0] PEDL87V2105-02 ML87V2105 Noise average value YAVRO[6:0] CAVRO[6:0] 87/103 ...
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... CAVRO [6:0], CMAXO[5: frames average 1 1 frame detection Noise detection reference position 0 1st line after valid data end line 1 2nd line after valid data end line PEDL87V2105-02 ML87V2105 BIT2 BIT1 BIT0 CNAMS YNAMS 1 0 88/103 ...
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... BIT6 BIT5 BIT4 BIT3 BIT6 BIT5 BIT4 BIT3 YBAVRO BIT6 BIT5 BIT4 BIT3 CBAVRO PEDL87V2105-02 ML87V2105 BIT2 BIT1 BIT0 BIT2 BIT1 BIT0 BIT2 BIT1 BIT0 YMAXO BIT2 BIT1 BIT0 CMAXO BIT2 ...
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... Color difference vertical blanking period noise detection flag. At NRDTON = 1, CBDTO is set to “1” if CBAVRO[6:0] > CAVR1[5:0] state continues in 4 frames. * When PNON = 0, noise detection is not performed for the valid data period, so the data in YAVRO1[6:0] = YBAVRO[6:0], CAVRO1[6:0] = CBAVRO[6:0], YDTO1 = YBDTO, CDTO1 = CBDTO is read. PEDL87V2105-02 ML87V2105 90/103 ...
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... BIT6 BIT5 BIT4 BIT3 REFSL CKINV 1 0 Output format mode 16-bit output I/O same format HREF pin output [1] 0 Horizontal reference signal 1 Color difference select signal 0 Effective area signal 1 Field pulse signal PEDL87V2105-02 ML87V2105 BIT2 BIT1 BIT0 DOSEL (Reserved) (Reserved) 91/103 ...
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... CKEN Initial value: 0; Setting range: Refer to Table R2-4-1 (4). Sets CLKO output enable. Table R2-4-1 (4) CLKO Output Setting CKEN During input 16-bit mode, IICLK = ICLK. CKSL CKINV CLKO output IICLK 0 1 Inverted IICLK 1 0 ICLK 1 1 Inverted ICLK PEDL87V2105-02 ML87V2105 92/103 ...
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... Sets HREF output polarity. Table R2-4-2 (3) HREF Polarity Setting HREFINV BIT6 BIT5 BIT4 (Reserved) (Reserved) (Reserved) OVS polarity 0 Positive polarity 1 Negative polarity OHS polarity 0 Positive polarity 1 Negative polarity HREF polarity 0 Positive polarity 1 Negative polarity PEDL87V2105-02 ML87V2105 BIT3 BIT2 BIT1 BIT0 HREF OVSINV OHSINV INV 93/103 ...
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... BIT6 BIT5 BIT4 BIT3 BIT6 BIT5 BIT4 BIT3 SHSDL ISYNC OVS and OHS output 0 Input delay output 1 Internally generated output OHS phase 0 Horizontal sync signal 1 Composite sync PEDL87V2105-02 ML87V2105 BIT2 BIT1 BIT0 HSSEL ISYNC BIT2 BIT1 BIT0 94/103 ...
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... Initial value: 0000_0000; Setting range: 0000_0000 to 1111_1111 TST1[15:8] Initial value: 0000_0000; Setting range: 0000_0000 to 1111_1111 Sets test mode: Normally fixed to 0000_0000. BIT6 BIT5 BIT4 BIT3 TST1 BIT6 BIT5 BIT4 BIT3 TST1 PEDL87V2105-02 ML87V2105 BIT2 BIT1 BIT0 BIT2 BIT1 BIT0 95/103 ...
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... BIT6 BIT5 BIT4 BIT3 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) PASS Mode 0 Normal operation 1 Data through All output pins Dependent on other settings (R656, DISEL, DOSEL) Disable Data reflection IVS, OVS synchronous 2 When I C-bus is set PEDL87V2105-02 ML87V2105 BIT2 BIT1 BIT0 OUTDS PASS 96/103 ...
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... RYNR RYNRM OFF 4 3 BIT6 BIT5 BIT4 BIT3 RCNR RCNRM OFF 4 3 BIT6 BIT5 BIT4 BIT3 RYMOF RNR2 OFF PEDL87V2105-02 ML87V2105 BIT2 BIT1 BIT0 RYNS BIT2 BIT1 BIT0 RCNS BIT2 BIT1 BIT0 RYLM BIT2 BIT1 BIT0 RCLM ...
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... RYMOF[3:1] Read value range: 000 to 111 Reads luminance motion compensation On/Off switching signal of internal operation state RYMOF[*] = YMOFF[*] in case either the auto mode is not set (NRAUTO = 0) or the follow-up is not set in the auto mode (AYMOFF[*] = 0). (Here 3.) PEDL87V2105-02 ML87V2105 98/103 ...
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... CO6 19 58 CI5 CO5 NR-FIFO 20 57 CI4 CO4 21 ML87V2105 56 CI3 CO3 22 54 CI2 CO2 23 53 CI1 CO1 24 52 CI0 CO0 25 51 HREF 47 IVS OVS 29 46 IHS OHS 30 45 CLKO 35 ICLK 16 PEDL87V2105-02 ML87V2105 SCAN CONVERTER (ML87V230X) DATA or OUT MPEG ENCODER CLK 99/103 ...
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... CO6(OPEN) NR-FIFO CI5(OPEN CO5(OPEN) CI4(OPEN) 21 ML87V2105 56 CO4(OPEN) CI3(OPEN CO3(OPEN) CI2(OPEN CO2(OPEN) CI1(OPEN CO1(OPEN) CI0(OPEN CO0(OPEN) 47 HREF(OPEN) IVS(OPEN OVS(OPEN) IHS(OPEN OHS(OPEN) 35 CLKO(OPEN) ICLK(27MHz) 16 PEDL87V2105-02 ML87V2105 SCAN CONVERTER (ML87V230X) DATA or OUT MPEG ENCODER CLK 100/103 ...
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... The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). PEDL87V2105-02 ML87V2105 (Unit: mm) Package material Epoxy resin ...
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... OKI Semiconductor REVISION HISTORY Document Date No. PEDL87V2105-01 Nov. 14, 2003 PEDL87V2105-02 Dec. 20, 2003 Page Previous Current Edition Edition – 103 Preliminary edition 1 103 103 Internal pull down, application schematic PEDL87V2105-02 ML87V2105 Description 102/103 ...
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... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. PEDL87V2105-02 ML87V2105 Copyright 2003 Oki Electric Industry Co., Ltd. 103/103 ...