wm8198scds-v Wolfson Microelectronics plc, wm8198scds-v Datasheet - Page 22

• Manufacturer Part Number: wm8198scds-v
• Description: 8 + 8 Bit Output 16-bit Cis/ccd Afe/digitiser
• Manufacturer: Wolfson Microelectronics plc

WM8198
LINE-BY-LINE OPERATION
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Certain linear sensors (e.g. Contact Image Sensors) give colour output on a line-by-line basis. i.e. a
full line of red pixels followed by a line of green pixels followed by a line of blue pixels. In order to
accommodate this type of signal the WM8198 can be set into Monochrome mode, with the input
channel switched by writing to control bits CHAN[1:0] between every line. Alternatively, the WM8198
can be placed into colour line-by-line mode by setting the LINEBYLINE control bit. When this bit is
set the green and blue processing channels are powered down and the device is forced internally to
only operate in MONO mode (because only one colour is sampled at a time) through the red channel.
Figure 20 shows the signal path when operating in colour line-by-line mode.
Figure 20 Signal Path When in Line-by-Line Mode
In this mode the input multiplexer and (optionally) the PGA/Offset register multiplexers can be auto-
cycled by the application of pulses to the RLC/ACYC input pin by setting the ACYCNRLC register bit.
See Figure 4 for detailed timing information. The multiplexers change on the first MCLK rising edge
after RLC/ACYC is taken high. A write to the auto-cycle reset register causes these multiplexers to
be reset; selecting the RINP pin and the RED offset/gain registers. Alternatively, all three
multiplexers can be controlled via the serial interface by writing to register bits INTM[1:0] to select the
desired colour. It is also possible for the input multiplexer to be controlled separately from the PGA
and Offset multiplexers. Table 4 describes all the multiplexer selection modes that are possible.
Table 4 Colour Selection Description in Line-by-Line Mode
RINP
GINP
BINP
FME
0
0
1
1
VRLC/VBIAS
ACYCNRLC
RLC
RLC
RLC
DAC
RLC
0
1
0
1
CL
4
INPUT
MUX
Internal,
no force mux
Auto-cycling,
no force mux
Internal,
force mux
Auto-cycling,
force mux
R
CDS
S
NAME
V
S
TIMING CONTROL
VSMP
R
G
B
R
G
B
OFFSET
MUX
PGA
MUX
MCLK
Input mux, offset and gain registers determined by
internal register bits INTM1, INTM0.
Input mux, offset and gain registers auto-cycled, RINP
→ GINP → BINP → RINP… on RLC/ACYC pulse.
Input mux selected from internal register bits FM1, FM0;
Offset and gain registers selected from internal register
bits INTM1, INTM0.
Input mux selected from internal register bits FM1, FM0;
Offset and gain registers auto-cycled, RED → GREEN
→ BLUE → RED… on RLC/ACYC pulse.
8
OFFSET
DAC
+
PGA
9
I/P SIGNAL
POLARITY
DESCRIPTION
ADJUST
+
PD, Rev 4.3, August 2008
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CONFIGURABLE
ADC
BIT
INTERFACE
16-
CONTROL
SERIAL
PORT
Production Data
DATA
I/O
OP[7:0]
SEN
SCK
SDI
RLC/ACYC
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