wm8198scds-v Wolfson Microelectronics plc, wm8198scds-v Datasheet
wm8198scds-v
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wm8198scds-v Summary of contents
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... WM8198 DVDD2 VRT VRX VRB VREF/BIAS + I/P SIGNAL POLARITY ADJUST DATA I/O M ADC PORT + U X I/P SIGNAL POLARITY ADJUST + I/P SIGNAL POLARITY CONFIGURABLE ADJUST SERIAL CONTROL INTERFACE DGND Production Data, August 2008, Rev 4.3 Copyright ©2008 Wolfson Microelectronics plc OEB OP[0] OP[1] OP[2] OP[3] OP[4] OP[5] OP[6] OP[7]/SDO SEN SCK SDI RLC/ACYC ...
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WM8198 DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 THERMAL PERFORMANCE .................................................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6 INPUT VIDEO SAMPLING ............................................................................................. 9 OUTPUT DATA TIMING ................................................................................................ ...
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... RINP 1 AGND2 2 DVDD1 3 OEB 4 VSMP 5 RLC/ACYC 6 MCLK 7 DGND 8 SEN 9 DVDD2 10 SDI 11 SCK 12 OP[0] 13 OP[1] 14 ORDERING INFORMATION TEMPERATURE DEVICE RANGE WM8198SCDS WM8198SCDS/ Note: Reel Quantity = 2,000 w 28 GINP 27 BINP 26 VRLC/VBIAS 25 VRX 24 VRT 23 VRB 22 AGND1 21 AVDD 20 OP[7]/SDO 19 OP[6] 18 OP[5] 17 OP[4] 16 OP[3] 15 OP[2] PACKAGE 28-lead SSOP ...
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WM8198 PIN DESCRIPTION PIN NAME TYPE 1 RINP Analogue input 2 AGND2 Supply 3 DVDD1 Supply 4 OEB Digital input 5 VSMP Digital input 6 RLC/ACYC Digital input 7 MCLK Digital input 8 DGND Supply 9 SEN Digital input 10 ...
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WM8198 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics ...
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WM8198 ELECTRICAL CHARACTERISTICS Test Conditions AVDD = DVDD1 = 5.0, DVDD2 = 3.3, AGND = DGND = 0V, T PARAMETER Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions) Conversion Rate Full-scale input voltage range, PGAMODE=0. (see Note ...
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WM8198 Test Conditions AVDD = DVDD1 = 5.0, DVDD2 = 3.3, AGND = DGND = 0V, T PARAMETER Programmable Gain Amplifier Resolution (PGAMODE=0) Gain (PGAMODE=0) Max gain, each channel (PGAMODE=0) Min gain, each channel (PGAMODE=0) Gain error, each channel (PGAMODE=0) ...
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WM8198 Test Conditions AVDD = DVDD1 = 5.0, DVDD2 = 3.3, AGND = DGND = 0V, T PARAMETER Supply Currents Total supply current − active (Three channel mode) Total supply current − active (Single channel mode) Total analogue supply current ...
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WM8198 INPUT VIDEO SAMPLING t MCLK t VSMPSU VSMP INPUT VIDEO Figure 1 Input Video Timing Note: 1. See Page 20 (Programmable VSMP Detect Circuit) for video sampling description. Test Conditions AVDD = DVDD1 = 5.0, DVDD2 = 3.3, AGND ...
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WM8198 OEB OP[7:0] Hi-Z Figure 3 Output Data Enable Timing Test Conditions AVDD = DVDD1 = 5.0, DVDD2 = 3.3, AGND = DGND = 0V, T PARAMETER Output propagation delay Output enable time Output disable time MCLK t ACYCSU RLC/ACYC ...
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WM8198 Test Conditions AVDD = DVDD1 = 5.0, DVDD2 = 3.3, AGND = DGND = 0V, T PARAMETER SCK period SCK high SCK low SDI set-up time SDI hold time SCK to SEN set-up time SEN to SCK set-up time ...
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WM8198 INTERNAL POWER ON RESET CIRCUIT Figure 6 Internal Power On Reset Circuit Schematic The WM8198 includes an internal Power-On-Reset Circuit, as shown in Figure 6, which is used to reset the digital logic into a default state after power ...
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WM8198 Figure 8 Typical Power up Sequence where DVDD1 is Powered before AVDD Figure 8 shows a typical power-up sequence where DVDD1 is powered up first assumed that DVDD1 is already up to specified operating voltage. When AVDD ...
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WM8198 DEVICE DESCRIPTION INTRODUCTION A block diagram of the device showing the signal path is presented on Page 1. The WM8198 samples up to three inputs (RINP, GINP and BINP) simultaneously. The device then processes the sampled video signal with ...
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WM8198 EXTERNAL VRLC Figure 9 Reset Level Clamping and CDS Circuitry If auto-cycling is not required, RLC can be selected by pin RLC/ACYC. Figure 10 illustrates control of RLC for a typical CCD waveform, with CL applied during the reset ...
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WM8198 R /CL (CDSREF = 00 /CL (CDSREF = 01 /CL (CDSREF = 10 /CL (CDSREF = 11) S Figure 11 Reset Sample and Clamp Timing For CIS type sensor signals, non-CDS processing is ...
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WM8198 Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01 (zero differential input voltage gives mid-range ADC output). OVERALL SIGNAL FLOW SUMMARY Figure 14 represents the processing of the video signal through the WM8198 RESET V ...
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WM8198 The resultant signal V PGA NODE: GAIN ADJUST The signal is then multiplied by the PGA gain. The PGA transfer characteristic varies with the value of the PGAMODE register bit. If PGAMODE = 0 (wide gain range PGA mode ...
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WM8198 OUTPUT FORMAT 8+8-bit multiplexed 4+4+4+4-bit (nibble) Table 2 Details of Output Data Shown in Figure 15 and Figure 16 CONTROL INTERFACE The internal control registers are programmable via the serial digital control interface. The register contents can be read ...
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WM8198 SCK SDI SEN SDO/ OP[7] OEB Figure 18 Serial Interface Register Read-back TIMING REQUIREMENTS To use this device a master clock (MCLK 12MHz and a per-pixel synchronisation clock (VSMP 6MHz are required. These ...
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WM8198 (VDEL = 000) INTVSMP (VDEL = 001) INTVSMP (VDEL = 010) INTVSMP (VDEL = 011) INTVSMP (VDEL = 100) INTVSMP (VDEL = 101) INTVSMP (VDEL = 110) INTVSMP (VDEL = 111) INTVSMP (VDEL = 000) INTVSMP (VDEL = 001) ...
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WM8198 LINE-BY-LINE OPERATION Certain linear sensors (e.g. Contact Image Sensors) give colour output on a line-by-line basis. i.e. a full line of red pixels followed by a line of green pixels followed by a line of blue pixels. In order ...
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WM8198 OPERATING MODES Table 5 summarises the most commonly used modes, the clock waveforms required and the register contents required for CDS and non-CDS operation. MODE DESCRIPTION CDS AVAILABLE Colour 1 Yes Pixel-by-Pixel Monochrome/ 2 Yes Colour Line-by-Line 3 Fast ...
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WM8198 OPERATING MODE TIMING DIAGRAMS The following diagrams show 8-bit multiplexed output data and MCLK, VSMP and input video requirements for operation of the most commonly used modes as shown in Table 5. The diagrams are identical for both CDS ...
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WM8198 Figure 23 Mode 3 Operation Figure 24 Mode 4 Operation w Production Data PD, Rev 4.3, August 2008 25 ...
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WM8198 16.5 MCLK PERIODS MCLK VSMP INPUT VIDEO OP[7: (DEL = 00) OP[7: (DEL = 01) ...
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WM8198 DEVICE CONFIGURATION REGISTER MAP The following table describes the location of each control bit used to determine the operation of the WM8198. The register map is programmed by writing the required codes to the appropriate addresses via the serial ...
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WM8198 REGISTER MAP DESCRIPTION The following table describes the function of each of the control bits shown in Table 6. REGISTER BIT BIT NO NAME(S) Setup 0 EN Register 1 1 CDS 2 MONO 3 SELPD 5:4 PGAFS[1:0] 6 MODE4 ...
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WM8198 REGISTER BIT BIT NO NAME(S) Setup 0 LINEBYLINE Register 4 1 ACYCNRLC 2 FME 3 RLCINT 5:4 INTM[1:0] 7:6 FM[1:0] Setup 0 VSMPDET Register 5 3:1 VDEL[2:0] 4 POSNNEG 7:5 Reserved Setup 3:0 SELDIS[3:0] Register 6 7:4 Reserved Special ...
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WM8198 REGISTER BIT BIT NO NAME(S) Offset DAC 7:0 DAC[7:0] (Red) Offset DAC 7:0 DAC[7:0] (Green) Offset DAC 7:0 DAC[7:0] (Blue) Offset DAC 7:0 DAC[7:0] (RGB) PGA gain 0 PGA[0] LSB (Red) PGA gain 0 PGA[0] LSB (Green) PGA gain ...
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WM8198 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS DVDD1 C1 DGND Video Inputs Timing Signals Interface Controls NOTES: 1. C1-9 should be fitted as close to WM8198 as possible. 2. AGND and DGND should be connected as close to WM8198 as possible. ...
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WM8198 PACKAGE DIMENSIONS DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm Dimensions Symbols (mm) MIN NOM A ----- A 0. 1.65 1. 0.22 c 0.09 D 9.90 10.20 ...
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... WM8198 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...