wm8199scds-v Wolfson Microelectronics plc, wm8199scds-v Datasheet - Page 16

no-image

wm8199scds-v

Manufacturer Part Number
wm8199scds-v
Description
20msps 16-bit Ccd Digitiser
Manufacturer
Wolfson Microelectronics plc
Datasheet
WM8199
OFFSET ADJUST AND PROGRAMMABLE GAIN
ADC INPUT BLACK LEVEL ADJUST
w
Figure 14 PGA Gain Characteristic
8
7
6
5
4
3
2
1
0
0
Gain register value (PGA[7:0])
64
Figure 13 Reset Sample and Clamp Timing
For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed
with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described
above. The VRLC/VBIAS pin is sampled by R
mode; non-CDS processing is achieved by setting switch 2 in the lower position, CDS=0.
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset
DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset for each
channel are independently programmable by writing to control bits DAC[7:0] and PGA[7:0].
The gain characteristic of the WM8199 PGA is shown in Figure 14. Figure 15 shows the maximum
device input voltage that can be gained up to match the ADC full-scale input range (3V).
In colour line-by-line mode the gain and offset coefficients for each colour can be multiplexed in order
(Red → Green → Blue → Red…) by pulsing the ACYC/RLC pin, or controlled via the FME,
ACYCNRLC and INTM[1:0] bits. Refer to the Line-by-Line Operation section for more details.
The output from the PGA should be offset to match the full-scale range of the ADC (3V). For
negative-going input video signals, a black level (zero differential) output from the PGA should be
offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. For positive going input
signal the black level should be offset to the bottom of the ADC range by setting PGAFS[1:0]=11.
Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01 (zero differential
input voltage gives mid-range ADC output).
R
R
R
R
128
S
S
S
S
/CL (CDSREF = 00)
/CL (CDSREF = 01)
/CL (CDSREF = 10)
/CL (CDSREF = 11)
192
MCLK
VSMP
VS
256
Figure 15 Peak Input Voltage to Match ADC Full-scale Range
4.5
3.5
2.5
1.5
0.5
s
4
3
2
1
0
at the same time as V
0
Gain register value (PGA[7:0])
64
128
s
samples the video level in this
PD, Rev 4.4, July 2008
192
Production Data
256
16

Related parts for wm8199scds-v