msm7630 Oki Semiconductor, msm7630 Datasheet - Page 49
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msm7630
Manufacturer Part Number
msm7630
Description
Universal Speech Processor
Manufacturer
Oki Semiconductor
Datasheet
1.MSM7630.pdf
(95 pages)
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• bit[1] H: Hold (read/write)
3.3 ECR: Extra Configuration Register
This register sets bus operation.
• bit[10] OX: Internal ROM (read-only)
• bit[9] AX: Internal RAM (read-only)
• bit[7] PM: Parity Mode (read/write)
• bit[3] A: All Internal ROM (read/write)
• bit[2] OV: Internal ROM Valid (read-only)
• bit[1] AV: Internal RAM Valid (read-only)
bit
This bit sets whether or not bus rights will be passed upon a CPU core bus rights request. This bit
will be "0" after reset.
This bit indicates whether or not internal ROM will be accessed in 2 clocks.
MSM7630 does not use this bit.
This bit indicates whether or not internal RAM will be accessed in 2 clocks.
MSM7630 does not use this bit.
This bit sets parity.
This bit will be "0" after reset.
MSM7630 does not use parity checking, so it ignores this field.
This bit sets whether or not internal ROM will be accessed instead of external ROM.
MSM7630 has no internal ROM, so this bit is always "0".
This bit shows whether internal ROM is enabled or disabled.
This bit is "0" for MSM7630.
This bit shows whether internal RAM is enabled or disabled.
This bit is "0" for MSM7630.
31
PM = 0
PM = 1
Even parity
Odd parity
11
10 9
O
X
A
X
8 7 6
0
M
P
BM
4
3
A
O
2
V
A
V
1
MSM7630
D
V
0
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