msm7630 Oki Semiconductor, msm7630 Datasheet - Page 4

• Manufacturer Part Number: msm7630
• Description: Universal Speech Processor
• Manufacturer: Oki Semiconductor

¡ Semiconductor
PIN DESCRIPTIONS
Symbol
TSTM2,1
D31-16
EXTINT
CAS0,1
UPORT
WR0,1
SRAM
PD7-0
TEST0
A23-0
PACK
DAO1
SCLK
PSTB
POBF
CLKA
STBY
ROM
PIOA
RXD
DSR
PIBF
RAS
TXD
DTR
RTS
PCS
RST
CTS
CLK
WE
RD
AS
SG
XO
3-state
3-state
Type
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
16-bit data bus. 8-bit devices are accessed through D31-24.
24-bit address bus. DRAM addresses are output from A13-0.
ROM select signal. ROM indicates that ROM space is assigned to the specified address.
It is used as a chip select signal.
SRAM select signal. SRAM indicates that SRAM space is assigned to the specified address.
It is used as a chip select signal.
Read signal. RD is active during both 8-bit and 16-bit reads.
Write signals. WR0 corresponds to writes from D31-24, and WR1 corresponds to
writes from D23-16.
Row address strobe. RAS is active during both 8-bit and 16-bit reads.
Column address strobe. CAS0 corresponds to accesses from D31-24, and CAS1
corresponds to accesses from D23-16.
Write enable. WE is active during writes to DRAM space as the DRAM write signal.
Address strobe.
Serial data output.
Serial data input.
Control signal indicating SIO can transmit and receive.
Input signal indicating that modem is in operable state.
SIO transmit request signal.
Input signal indicating that modem can transmit.
Synchronous transfer clock output.
Parallel port data input/output.
Parallel port read signal. Set high for Centronics interface.
Parallel port write signal. Strobe signal for Centronics interface.
Parallel port chip select signal.
Parallel port address signal. Selects data or status during an access.
Output port buffer full. Indicates that data has been set in the output buffer.
Input port buffer full. Indicates that there is data in the input buffer.
Busy output signal for Centronics interface.
General flag output signal.
Connects with SG.
D/A converter output.
Signal ground. Connects with TEST0.
Clock input signal.
Clock signal. Inverse of CLK.
Internal clock signal.
Reset input.
Standby signal. STBY suspends operation and places the MSM7630 in a standby state.
External interrupt signal.
Test mode select input signal.
Description
MSM7630
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