ml7074-003 Oki Semiconductor, ml7074-003 Datasheet - Page 29

• Manufacturer Part Number: ml7074-003
• Description: Dual Echo Canceler & Noise Canceler With Dual Codec For Hands-free Msm7731-02dual Echo Canceler & Noise Canceler With Dual Codec For Hands-free
• Manufacturer: Oki Semiconductor

(2) CR1
B7
B6, B5, B4, B3
B2
B1
B0
Note:
OKI Semiconductor
Initial Value
CR1
NCSEL2
Internal data memory write control
Echo Canceler I/O PAD control
Slope filter control
Noise attenuation selection control
In internal data memory, the data set in CR8 (D15 to D8) and CR9 (D7 to D0) is written to the memory
address set in CR6 (A15 to A8) and CR7 (A7 to A0).
Writing is possible only during the initial mode.
For further details, refer to the internal data memory access method.
This bit controls the attenuators (LPADL/A) provided in the SinL/A inputs and the amplifiers
(GPADL/A) provided in the SoutL/A outputs of the echo canceler. Levels are set by the CR10 register,
and ±18, ±12, ±6 and 0 dB can be set. The default value is ±12 dB. Use this bit when the echo return loss
(value of returned echo) is amplified. If the pin setting is changed, the coefficient reset must be activated
by either the RST pin or the RST bit (CR0-B6). Because data is read by this bit in synchronization with
the rising edge of the SYNC signal, hold the data in the bit for 250 µs or longer. This bit is internally
ORed with the GLPADTHR pin.
This bit controls operation of the transmit slope filter. In the “through mode”, the filter is halted and data
is output directly. The slope filter decreases noises of low frequencies and improves the speech quality.
Refer to the frequency characteristics of slope filter. Because data is read by this bit in synchronization
with the rising edge of the SYNC signal, hold the data in the bit for 250 µs or longer. This bit is
internally ORed with the SLPTHR pin.
This bit selects the noise attenuation of the noise canceler. In the “through mode”, the noise canceler is
halted and data is output directly. In the “normal mode” the noise canceler operates normally. Since the
noise attenuation in the normal mode is selected after the initial mode has been released, the change of
the noise attenuation during normal operation is invalid. If the noise attenuation is changed, reset must
be activated by the RDN/RST pin or the PDN/RST bit (CR0-B7). Changing to the through mode during
normal operation and returning to the normal mode are possible. This bit is internally ORed with
NCSEL1 pin. (Refer to the NCSEL2 pin of CR12-B2.)
the noise attenuation appropriate to the sound quality.
0
1
1
0
Since there is a trade-off between noise attenuation and sound quality after canceling the noise, select
DMWR
B7
0
Reserved bits.
NCSEL1
B6
—
0
0
1
0
1
Modification of initial values is inhibited.
0: normal mode (slope filter operation) 1: “through mode”
B5
—
0
Through Mode
Normal Mode
Normal Mode
Normal Mode
0: write inhibited
0: “through mode” 1: normal mode
0: normal mode
NC Mode
B4
—
0
B3
—
0
1: write
1: “through mode”
Attenuation (dB)
GLPADTHR
13.5
17
—
8
B2
0
SLPTHR
B1
0
FEDL7731-02-11
Quality
MSM7731-02
Better
Best
—
NCSEL1
B0
0
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