73k224bl ETC-unknow, 73k224bl Datasheet - Page 26

• Manufacturer Part Number: 73k224bl
• Description: Single-chip Modem Integrated Hybrid
• Manufacturer: ETC-unknow

73K224BL
V.22bis/V.22/V.21/Bell 212A/103
Single-Chip Modem w/ Integrated Hybrid
DYNAMIC CHARACTERISTICS AND TIMING
* All timing parameters are targets and not guaranteed.
** Control for setup is the falling edge of RD or WR . Control for hold is the falling edge of RD or the rising
NOTE: Asserting ALE, CS , and RD or WR concurrently can cause unintentional register accesses. When
PARAMETER
TIMING
(Refer to Timing Diagrams)
TAL
TLA
TLC
TCL
TRD
TLL
TRDF
TRW
TWW
TDW
TWD
TCKD
TCKW (serial mode)
TDCK (serial mode)
TAC (serial mode)
TCA (serial mode)
TWH (serial mode)
edge of WR .
using non-8031 compatible processors, care must be taken to prevent this from occurring when
designing the interface logic.
AD0-AD7
CS
CONDITION
*
CS /Address setup before ALE Low
CS
Address hold after ALE Low
ALE Low to RD/WR Low
RD/WR Control to ALE High
Data out from RD Low
ALE width
Data float after RD High
RD width
WR width
Data setup before WR High
Data hold after WR High
Data out after EXCLK Low
WR after EXCLK Low
Data setup before EXCLK Low
Address setup before control**
Address hold after control**
Data Hold after EXCLK
(continued)
26
MIN
150
150
150
12
10
10
15
50
15
12
50
50
50
0
0
0
NOM
MAX
200
70
50
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns