73k224bl ETC-unknow, 73k224bl Datasheet - Page 17

• Manufacturer Part Number: 73k224bl
• Description: Single-chip Modem Integrated Hybrid
• Manufacturer: ETC-unknow

CONTROL REGISTER 2
BIT
D0
D1
D2
D3
D4
D5
D6
D7
ADDR
CR2
100
D7
0
Not used at this time
SPEC REG
RESET DSP
Transmit S1
Train Inhibit
ACCESS
Equalizer
Register
16 Way
Call Init
Special
Access
Enable
NAME
D6
CALL INIT
D5
CONDITION
Single-Chip Modem w/ Integrated Hybrid
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
TRANSMIT S1
D4
17
DESCRIPTION
The adaptive equalizer is in its initialized state.
The adaptive equalizer is enabled. This bit is used in
handshakes to control when the equalizer should
calculate its coefficients.
The adaptive equalizer is active.
The adaptive equalizer coefficients are frozen.
The DSP is inactive and all variables are initialized.
The DSP is running based on the mode set by other
control bits.
The receiver and transmitter are using the same decision
plane (based on the modulator control mode).
The receiver, independent of the transmitter, is forced
into a 16 point decision plane. Used for QAM
handshaking.
The transmitter when placed in alternating mark/space
mode transmits 0101...... scrambled or not dependent on
the bypass scrambler bit.
When this bit is 1 and only when the transmitter is placed
in alternating mark/space mode by CR1 bits D7, D6, and
in DPSK or QAM, an unscrambled repetitive double di-bit
pattern of 00 and 11 at 1200 bit/s (S1) is sent.
The DSP is set-up to do demodulation and pattern
detection based on the various mode bits. Both answer
tones are detected in demodulation mode concurrently;
TR-D0 is ignored.
The DSP decodes unscrambled mark, answer tone and
call progress tones.
Normal CR3 access.
Setting this bit and addressing CR3 allows access to the
special register (see the special register for details).
Only write zero to this bit.
V.22bis/V.22/V.21/Bell 212A/103
16 WAY
D3
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
DSP
DSP
DSP
DSP
DSP
DSP
DSP
DSP
D2
INHIBIT
TRAIN
D1
73K224BL
EQUALIZER
ENABLE
D0