hsp50110 Intersil Corporation, hsp50110 Datasheet - Page 12

• Manufacturer Part Number: hsp50110
• Description: Digital Quadrature Tuner
• Manufacturer: Intersil Corporation

CLK by a programmable factor of 2, 4, or 8. When the
programmable clock factor is 1, IOUT9 is pulled high, and the
CLK signal should be used as the clock. The beginning of a
serial data word is signaled by the assertion of DATARDY one
serial clock before the first bit of the output word. In I followed
by Q Mode, DATARDY is asserted prior to each 16-bit data
word. For added flexibility, the Formatter may be configured to
output the data words in either MSB or LSB first format
NOTE: Assumes data is being output LSB first.
NOTE: Assumes data is being output MSB first.
DATARDY
DATARDY
FIGURE 15. SERIAL TIMING (SIMULTANEOUS I/Q MODE)
IOUT9
IOUT0
IOUT0/
QOUT0
INPUT
FIGURE 16. SERIAL TIMING (I FOLLOWED BY Q MODE)
IOUT9
DATARDY may be programmed active high or low.
-2
2
2
-1
-9
0
DATARDY
LEADS 1st BIT
SYNTHESIZER/
G = 0.9990
G = -6.02dB
G
dB
MIXER
MSB
= 0dB
LSB
DATARDY LEADS 1st BIT
RND
2
-2
2
2
-10
I DATA WORD
-1
0
1
G
dB
12
LSB
SCALER
G = 2
FIGURE 17. GAIN DISTRIBUTION AND INTERMEDIATE BIT WEIGHTINGS
= -216.74dB
CIC
(0.0625 STEPS)
MSB
-36
BINARY POINT
0
BY 1 IN LSB OF DATA WORD
MANTISSA
1.0 - 1.9375
I OUTPUT IDENTIFIED
-2
2
-46
-35
AGC GAIN
G
dB
1
= G
EXPONENT
G
G = 1.0 - 1.9375*2
AGC
SHIFTER
MSB
2
0
Q DATA
BIT RANGE OF DATA PATH
WORD
-2
.
+
7
LSB
HSP50110
RND
2
-2
2
2
CIC BARREL
-46
-1
0
8
SHIFTER
G
2
dB
0
N = 1, 3
70
-2
= 20log[R]
= 20log[f
63
G = 2
Gain Distribution
The gain distribution in the DQT is shown in Figure 17. These
gains consist of a combination of fixed, programmable, and
adaptive gains. The fixed gains are introduced by processing
elements like the Synthesizer/Mixer and CIC Filter. The
programmable and adaptive gains are set to compensate for
the fixed gains as well as variations in input signal strength.
The bit range of the data path between processing elements
is shown in Figure 17. The quadrature inputs to the data path
are 10-bit fractional two’s complement numbers. They are
multiplied by a 10-bit quadrature sinusoid and rounded to
12-bits in the Synthesizer/Mixer. The I and Q legs are then
scaled by a fixed gain of 2
case gain of the CIC filter. Next, a gain block with an adaptive
and programmable component is used to set the output signal
level within the desired range of the 10-bit output (see Setting
DQT Gains Section). The adaptive component is produced by
the AGC and has a gain range from 1.0 to 1.9375*2
programmable component sets the gain range of the CIC
shifter which may range from 2
when setting the AGC gain limits and the CIC Shifter gain
since the sum of these gains could shift the CIC Scaler output
beyond the bit range (-2
CIC Filter introduces a gain factor given by R
decimation rate of the filter and N is the CIC order. The CIC
order is either 1 (integrate and dump filter) or 3. Depending on
configuration, the CIC Filter introduces a gain factor from 2
2
an 11-bit window between bit positions 2
outside this range saturate to these 11 bits. The
Compensation Filter introduces a final gain factor of 1.0, 0.65,
36
FILTER
CIC
S
. The output of the CIC Filter is then rounded and limited to
0
/f
N
- 2
D
(R
]
N
36
N
RND
-2
2
2
)
2
-1
-9
0
8
G
dB
LIMIT
= 0dB
2
2
-2
G = 1.0, 0.65, 0.77
COMPENSATION
2
-1
-9
0
1
0dB BYPASS
8
(BYPASS, x/sin(x), (x/sin(x))
to 2
-3.74dB
-2.27dB
-36
FILTER
G
GAIN
dB
-46
to compensate for the worst
=
0
) of the CIC Filter input. The
to 2
RND
2
-2
2
2
-9
-1
63
0
3
G
. Care must be taken
dB
1
LIMIT
= 0dB
to 2
N
-9
where R is the
-2
2
2
. Values
-1
-9
3
0
OUTPUT
7
. The
0
to