hsp50110 Intersil Corporation, hsp50110 Datasheet
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hsp50110
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hsp50110 Summary of contents
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... Satellite Receivers and Modems • Complex Upconversion/Modulation • Tuner for Digital Demodulators N response of the • Digital PLLs • Related Products: HSP50210 Digital Costas Loop; A/D Products HI5703, HI5746, HI5766 • HSP50110/210EVAL Digital Demod Evaluation Board Ordering Information PART NUMBER HSP50110JC-52 HSP50110JI-52 LOOP FILTER GCA ...
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... COFSYNC. COFSYNC I Carrier Offset Frequency Sync. This signal is asserted one CLK cycle before the MSB of the offset frequency data word (see Serial Interface Section). 2 HSP50110 HSP50110 (PLCC) TOP VIEW ...
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... AGC loop around the A/D converter. This type of AGC sets the level based on the median value on the input. CLK I Clock. All I/O’s with the exception of the output enables and the microprocessor interface are synchronous to clock. 3 HSP50110 DESCRIPTION ...
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... OFFSET † LOTP Indicates data downloaded via microprocessor interface † FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF HSP50110 compares the input signal magnitude to a programmable level and generates an error signal. The error signal can be externally averaged to set the gain of an amplifier in front of the A/D which closes the AGC loop. The output signal level is maintained by an internal AGC loop closed around the Low Pass Filtering ...
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... For real inputs, the magnitude detector reduces absolute value detector with negligible error. 5 HSP50110 Note: an external AGC loop using the Input Level Detector may go unstable for a real sine wave input whose frequency is exactly one quarter of the sample rate (F /4) ...
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... The level of the Mixer output is gain adjusted by an AGC closed around the Low Pass Filtering. The AGC provides the coarse gain correction necessary to help maintain the output of the HSP50110 at a signal level which maintains an acceptable dynamic range. The AGC consists of a Level Detector which generates an error signal, a Loop Gain multiplier which amplifi ...
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... Figure 3 (see AGC Control Register, Table 8). The format for the limits is the same as the format of the eight 7 HSP50110 most significant bits of the Loop Filter Accumulator. Examples of how to set the limits for a specific output signal level are provided in the “Setting DQT Gains” Section below. ...
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... The overall passband ripple S degrades slightly for decimation rates of less than 10. Some 8 HSP50110 examples of compensation filter performance for the Integrate and dump and third order CIC filter are shown overlaid on the frequency responses of the uncompensated filters in Figure 6 (EQ. 8) and Figure 7 ...
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... SAMPLE TIMES FIGURE 10. ALIAS PROFILE: 3RD ORDER CIC, NO COMPENSATION 9 HSP50110 Consider a digital filter with sampling frequency fs, whose frequency response shown in Figure 12A, the top spectrum. At first glance the usable bandwidth would appear to be the 3dB bandwidth of the main lobe. This filter ...
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... However, for configurations which use the third order CIC filter HSP50110 constant for decimation factors of over ~50. A summary of equivalent IF B decimation rates is given in Table 3. These noise bandwidths are provided so that output SNR can be calculated from input SNR ...
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... Low Pass Filter s Section, SCF is the 32-bit value loaded into the Sampler 11 HSP50110 Center Frequency Register, and SOF is the 32-bit value loaded into the Sample Offset Frequency Register. The SCF Register is loaded through the Microprocessor Interface (see † ...
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... RND G = -6.02dB FIGURE 17. GAIN DISTRIBUTION AND INTERMEDIATE BIT WEIGHTINGS 12 HSP50110 Gain Distribution The gain distribution in the DQT is shown in Figure 17. These gains consist of a combination of fixed, programmable, and adaptive gains. The fixed gains are introduced by processing elements like the Synthesizer/Mixer and CIC Filter. The programmable and adaptive gains are set to compensate for the fixed gains as well as variations in input signal strength ...
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... HSP50110 NOTE: 10log related. Thus, the minimum input signal will then be -42.96dB below . full scale (-30.96dB -12dB for A/D backoff). Note: in this example the symbol rate is assumed to be one half of the output sample rate (i.e., there are 2 samples per symbol). ...
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... AGC gain range of 3.05dB < G <12.72dB. AGC 14 HSP50110 Basic Architectural Configurations Detailed architectural diagrams are presented in Figures 18 through 20 for the basic configurations, Integrate/Dump filtering with optional compensation, 3rd Order CIC filtering with optional compensation, and Decimating Filter bypass. Only one of the data paths is shown since the processing on either the inphase or quadrature legs is identical ...
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R R HI/ SIN/COS CIC SCALER LEVEL VECTOR FROM -36 2 DETECT CARRIER NCO IIN0- QIN0 COMPLEX MULTIPLIER MANTISSA (1.0 ...
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... The HSP50110 is configured by loading a series of nine 32-bit Control Registers via the Microprocessor Interface. A Control Register is loaded by first writing the four 8-bit Holding Registers and then writing the destination address to the Address Register as shown in Figure 23. The Control Register Address Map and bit definitions are given in Tables 6-15 ...
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... CLK. They are shown that way to clarify the illustration. FIGURE 24. CENTER FREQUENCY CONTROL REGISTER LOADING SEQUENCE USING CF LOAD 17 HSP50110 Configuration Register can be loaded one CLK after CFLD has been loaded on the rising edge of CLK. The Microprocessor Interface can be used to read the upper 8 bits of the AGC Loop Filter Accumulator. The procedure for reading the Loop Accumulator consists of fi ...
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... Programmable part of Loop Gain word (see AGC Section). The Loop Gain value increments or decre- Gain ments the Loop Filter’s Accumulator at bit positions 2 gain is loaded into bit positions 31-24 (31 is the MSB and maps to the 2 (GGGGGGGG) 18 HSP50110 TABLE 6. CENTER FREQUENCY REGISTER DESTINATION ADDRESS = ...
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... Re-Sampler Section and Low Pass Filtering Section). 22-21 Compensation 0 0 x/sinx filtering. Filtering 0 1 (x/sinx bypass compensation filter. (See Low Pass Filtering Section). 19 HSP50110 TABLE 9. I/O FORMATTING/CONTROL DESTINATION ADDRESS = 4 DESCRIPTION Serial Output Clock Rate CLK (Serial Output Clock Pin = High) Clk/2 CLK/4 CLK/8 ...
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... Cascode CIC Filter Accumulator • AGC Loop Filter Accumulator • Serial Output Shifter Counter • Serial Output Clock Logic • ReSampler NCO Carry Output Programmable Divider 31-15 Reserved. 20 HSP50110 DESTINATION ADDRESS = 5 DESCRIPTION TABLE 11. CHIP CONFIGURATION REGISTER DESTINATION ADDRESS = 6 DESCRIPTION threshold. Bits 28:24. ...
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... Processing, Vol. ASSP-29 No. 2, April 1981. [2] Samueli, Henry “The Design of Multiplierless FIR filters for Compensating D/A Converter Frequency Response Distortion”, IEEE Transaction Circuits and Systems, Vol. 35, No. 8, August 1988. 21 HSP50110 TABLE 12. PHASE OFFSET REGISTER DESTINATION ADDRESS = 7 DESCRIPTION TABLE 13. TEST REGISTER DESTINATION ADDRESS = 8 DESCRIPTION TABLE 14 ...
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... Hold Time IIN9-0, QIN9-0, ENI, PH1-0, CFLD, COF, SOF, COFSYNC, and SOFSYNC from CLK Setup Time A0-2, C0-7 to Rising Edge of WR Hold Time A0-2, C0-7 from Rising Edge HSP50110 Thermal Information Thermal Resistance (Typical, Note 3) +0.5V PLCC Package ...
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... Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes. 9. Set time to ensure action initiated SERCLK will be seen by a particular clock. AC Test Load Circuit † Test head capacitance. 23 HSP50110 5.0V 5 ...
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... Waveforms t WRL C0-7, A0-2 FIGURE 26. TIMING RELATIVE 2.0V 0.8V FIGURE 28. OUTPUT RISE AND FALL TIMES 24 HSP50110 IIN9-0, QIN9-0, ENI, PH1-0, CFLD, COF, SOF, COFSYNC, t WRH t WH OEI OEQ t RF OUTI9-0 OUTQ9-0 t RDL RD C0 RDO ROD FIGURE 30. TIMING RELATIVE TO READ ...
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... For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation 2401 Palm Bay Rd., Mail Stop 53-204 Palm Bay, FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7240 25 HSP50110 N84.1.15 0.004 (0.10 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE 0.025 (0.64) R 0.045 (1.14) SYMBOL ...