micrf507ymltr Micrel Semiconductor, micrf507ymltr Datasheet - Page 19

• Manufacturer Part Number: micrf507ymltr
• Description: 470mhz To 510mhz Low-power Fsk Transceiver With +10dbm Power Amplifier
• Manufacturer: Micrel Semiconductor

In sync mode (Sync_en bit set to 1), the transmitted bit
stream is clocked with the precision of the MICRF507’s
crystal
requirements on the data source. During reception, the
synchronizer ensures that transitions of DATAIXO occur
only at rising edges of DATACLK, without edge jitter or
internal glitches. Receiver sensitivity values given in the
Electrical Characteristics table are measured with Sync_en
= 1; with Sync_en = 0, as much as 3-6 dB of sensitivity
could be lost.
Sync_en = 0
When Sync_en = 0, the input signal at DATAIXO
modulates the transmitter directly during transmission and
the output signal from DATAIXO is the raw demodulator
output. DATACLK remains fixed at a logic low level during
both transmission and reception.
Sync_en = 1
During transmission when Sync_en = 1 the data bit stream
entering DATAIXO is buffered with a flip-flop strobed at the
rising edge of BITRATE_CLK, and the output of the flip-
flop modulates the transmitter. BITRATE_CLK is brought
out at the DATACLK output. Figure 10 shows the
relationship of DATACLK and DATAIXO transitions.
During reception, the bit synchronizer recovers the
received signal’s clock. This recovered clock strobes a flip-
flop that samples in mid-bit-period the demodulated and
filtered bit stream. The DATACLK output brings out the
March 2010
Micrel, Inc.
DATACLK
DATAIXO
Figure 10. Data Interface in Transmit Mode
Transmit
Receive
oscillator,
Mode
Sync_en
which
0
1
0
1
Direction
Output
Output
Output
Output
relaxes
Table 8. Synchronizer Mode and Data Interface
timing
DATACLK
Signal
0
BitRate clock
0
Clock recovered by bit
synchronizer
accuracy
19
recovered clock. DATAIXO (an output during reception)
brings out the synchronized data stream, which has its
transitions at rising edges of DATACLK. See Figure 11.
By being in control of bit timing, the MICRF507 is
effectively the “master.” For maximum timing margin, the
microcontroller, as the “slave,” can present or sample
(during transmit and receive, respectively) each new bit at
the DATAIXO pin at falling edges of DATACLK.
Additional Considerations in the Use of Synchronizer
(Sync_en = 1)
Two clock signals, BITRATE_CLK and BITSYNC_CLK,
must
synchronizer. BITRATE_CLK, used in transmission, must
be
BITSYNC_CLK, used in reception, must have a frequency
16 times the bit rate. These frequencies are controlled by
the crystal oscillator frequency and the settings of register
fields, as described in the “Clock Generation” section. Bit
clocking of the incoming signal must agree with the
receiver’s local clocking within
PPM or better crystals). For example, if f
16x19.231kbps, the incoming bit rate can be between
0.975x19.231kbps to 1.025x19.231kbps.
All incoming messages must start with a 0101… preamble
so that the synchronizer can acquire the incoming clock. A
24-bit preamble is typically used; a minimum of 22 bits is
required.
DATACLK
DATAIXO
Direction
Input
Input
Output
Output
set
be
Figure 11. Data Interface in Receive Mode
to
properly
a
Raw output from demodulator
Signal/Function
Modulates carrier directly
(asynchronously)
Sampled at rising edge of BitRate
clock; latched output modulates
carrier
Filtered and latched demodulator
output; transitions occur at rising
edge of DATACLK
frequency
DATAIXO
programmed
equal
±
2.5% (easily met with 100
to
when
M9999-032210-B
the
BITSYNC_CLK
MICRF507
using
bit
rate.
the
is