la-ispmach4032v Lattice Semiconductor Corp., la-ispmach4032v Datasheet - Page 7

• Manufacturer Part Number: la-ispmach4032v
• Description: 3.3v/1.8v In-system Programmable Superfast High Density Plds Tm
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Clock Enable Multiplexer
Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the fol-
lowing four sources:
Initialization Control
The LA-ispMACH 4000V/Z automotive family architecture accommodates both block-level and macrocell-level set
and reset capability. There is one block-level initialization term that is distributed to all macrocell registers in a GLB.
At the macrocell level, two product terms can be “stolen” from the cluster associated with a macrocell to be used for
set/reset functionality. A reset/preset swapping feature in each macrocell allows for reset and preset to be
exchanged, providing flexibility.
Note that the reset/preset swapping selection feature affects power-up reset as well. All flip-flops power up to a
known state for predictable system initialization. If a macrocell is configured to SET on a signal from the block-level
initialization, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a
signal from the block-level initialization or is not configured for set/reset, then that macrocell will RESET on power-
up. To guarantee initialization values, the V
delay time has elapsed.
GLB Clock Generator
Each LA-ispMACH 4000V/Z automotive device has up to four clock pins that are also routed to the GRP to be used
as inputs. These pins drive a clock generator in each GLB, as shown in Figure 6. The clock generator provides four
clock signals that can be used anywhere in the GLB. These four GLB clock signals can consist of a number of com-
binations of the true and complement edges of the global clock signals.
Figure 6. GLB Clock Generator
• Block CLK3
• PT Clock
• PT Clock Inverted
• Shared PT Clock
• Ground
• PT Initialization/CE
• PT Initialization/CE Inverted
• Shared PT Clock
• Logic High
CLK0
CLK1
CLK2
CLK3
CC
rise must be monotonic, and the clock must be inactive until the reset
LA-ispMACH 4000V/Z Automotive Family Data Sheet
7
Block CLK0
Block CLK1
Block CLK2
Block CLK3