gs840e32agt-180i GSI Technology, gs840e32agt-180i Datasheet - Page 9
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gs840e32agt-180i
Manufacturer Part Number
gs840e32agt-180i
Description
256k X 18, 128k X 32, 128k X 36 4mb Sync Burst Srams
Manufacturer
GSI Technology
Datasheet
1.GS840E32AGT-180I.pdf
(32 pages)
Rev: 1.14 10/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
BGA Pin Description
ADSP, ADSC
Symbol
A
E
DQP
DQP
DQP
DQP
V
ADV
DQ
LBO
DQ
DQ
GW
V
V
BW
DQ
NC
0
CK
1
B
B
B
B
ZZ
FT
DDQ
E
A
G
, A
, E
DD
SS
A
B
C
D
2
A
B
D
A
B
C
D
1
3
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
In
In
In
In
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
9/32
Address Strobe (Processor, Cache Controller); active low
Address field LSBs and Address Counter Preset Inputs
Burst address counter advance enable; active low
Global Write Enable—Writes all bytes; active low
Byte Write signal for data inputs DQ
Byte Write signal for data inputs DQ
Byte Write signal for data inputs DQ
Byte Write signal for data inputs DQ
Byte Write—Writes all enabled bytes; active low
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Sleep Mode control; active high
Clock Input Signal; active high
Output driver power supply
Output Enable; active low
Chip Enable; active high
9th Data I/O Pin; Byte C
9th Data I/O Pin; Byte D
9th Data I/O Pin; Byte A
9th Data I/O Pin; Byte B
Chip Enable; active low
I/O and Core Ground
Core power supply
Description
Address Inputs
No Connect
GS840E18/32/36AT/B-180/166/150/100
C
D
A
B
; active low
; active low
; active low
; active low
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