gal20vp8 Lattice Semiconductor Corp., gal20vp8 Datasheet - Page 15

• Manufacturer Part Number: gal20vp8
• Description: High-speed E2 Cmos Pld Generic Array Logic? Gal
• Manufacturer: Lattice Semiconductor Corp.

Circuitry within the GAL20VP8 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (
state on the registered output pins (if they are enabled) will always
be high on power-up, regardless of the programmed polarity of
the output pins. This feature can greatly simplify state machine
design by providing a known state on power-up. The timing dia-
gram for power-up is shown above. Because of the asynchro-
Vref = 3.1V
Power-Up Reset
Input/Output Equivalent Schematics
PIN
PIN
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
Typical Input
Active Pull-up
FEEDBACK/EXTERNAL
INTERNAL REGISTER
Circuit
OUTPUT REGISTER
Vref
t
pr, 1 s MAX). As a result, the
Q - OUTPUT
Vcc
CLK
Vcc
Vcc
Vcc (min.)
15
t
nous nature of system power-up, some conditions must be met
to provide a valid power-up reset of the GAL20VP8. First, the V
rise must be monotonic. Second, the clock input must be at static
TTL level as shown in the diagram during power up. The registers
will reset within a maximum of
eration, avoid clocking the device until all input and feedback path
setup times have been met. The clock must also meet the mini-
mum pulse width requirements.
Vref = 3.1V
pr
Data
Output
Specifications GAL20VP8
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
Feedback
Tri-State
Control
t
wl
t
su
Typical Output
Vcc
t
pr time. As in normal system op-
Active Pull-up
Circuit
Feedback
(To Input Buffer)
Vref
PIN
PIN
CC