gal20vp8 Lattice Semiconductor Corp., gal20vp8 Datasheet - Page 13
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gal20vp8
Manufacturer Part Number
gal20vp8
Description
High-speed E2 Cmos Pld Generic Array Logic? Gal
Manufacturer
Lattice Semiconductor Corp.
Datasheet
1.GAL20VP8.pdf
(17 pages)
Output Load Conditions (see figure)
Note: fmax with external feedback is calculated from measured
tsu and tco.
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
3-state levels are measured 0.5V from steady-state active
level.
f
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
max Descriptions
Test Condition
A
B
C
Active High
Active Low
Active High
Active Low
f
max with External Feedback 1/(
LOGIC
ARRAY
LOGIC
ARRAY
t
su +
t
f
su
max with No Feedback
t
h
500
500
500
R
1
REGISTER
REGISTER
CLK
CLK
500
500
500
500
500
R
3ns 10% – 90%
t
2
co
t
GND to 3.0V
See Figure
su+
1.5V
1.5V
t
co)
50pF
50pF
50pF
5pF
5pF
C
L
13
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
FROM OUTPUT (O/Q)
UNDER TEST
*C
Specifications GAL20VP8
f
max with Internal Feedback 1/(
L
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
LOGIC
ARRAY
R
2
t
cf
t
+5V
pd
REGISTER
CLK
R
1
t
C *
su+
L
TEST POINT
t
cf)