lcmxo2-2000ze-1uwg49itr1 Lattice Semiconductor Corp., lcmxo2-2000ze-1uwg49itr1 Datasheet - Page 98

• Manufacturer Part Number: lcmxo2-2000ze-1uwg49itr1
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
• The on-chip differential input termination resistor value is higher than intended. It is approximately 200 as
• SRAM CRC Error Detection logic may not produce the correct result when it is run for the first time after configu-
• Under certain conditions, IIH exceeds data sheet specifications. The following table provides more details:
• The user SPI interface does not operate correctly in some situations. During master read access and slave write
• In GDDRX2, GDDRX4 and GDDR71 modes, ECLKSYNC may have a glitch in the output under certain condi-
• When using the hard I
• PLL Lock signal will glitch high when coming out of standby. This glitch lasts for about 10
• Dual boot only available on HC devices, requires tying VCC and VCCIO2 to the same 3.3V or 2.5V supply.
VPAD > VCCIO
VPAD = VCCIO
VPAD = VCCIO
VPAD < VCCIO
opposed to the intended 100. It is recommended to use external termination resistors for differential inputs. The
on-chip termination resistors can be disabled through Lattice design software.
ration. To use this feature, discard the result from the first operation. Subsequent operations will produce the cor-
rect result.
access, the last byte received does not generate the RRDY interrupt.
tions, leading to possible loss of synchronization.
low.
Condition
2
C IP core, the I
Clamp
OFF
OFF
OFF
ON
2
C status registers I2C_1_SR and I2C_2_SR may not update correctly.
Pad Rising
IIH Max.
10µA
10µA
1mA
1mA
5-16
Pad Falling
IIH Min.
-10µA
-10µA
-1mA
-1mA
Steady State Pad
MachXO2 Family Data Sheet
High IIH
10µA
10µA
1mA
1mA
Ordering Information
µ
sec before returning
Steady State Pad
Low IIL
10µA
10µA
10µA
10µA