lcmxo2-2000ze-1uwg49itr1 Lattice Semiconductor Corp., lcmxo2-2000ze-1uwg49itr1 Datasheet - Page 23

• Manufacturer Part Number: lcmxo2-2000ze-1uwg49itr1
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
These gearboxes have three stage pipeline registers. The first stage registers sample the high-speed input data by
the high-speed edge clock on its rising and falling edges. The second stage registers perform data alignment
based on the control signals UPDATE and SEL0 from the control block. The third stage pipeline registers pass the
data to the device core synchronized to the low-speed system clock. Figure 2-16 shows a block diagram of the
input gearbox.
Figure 2-16. Input Gearbox
D
ECLK0/1
UPDATE
SEL0
Q21
Q43
Q65
Q_6
Q32
Q54
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
cdn
Q0_
Q21
Q43
Q65
Q_6
Q54
Q32
Q10
Q10
Q32
Q54
Q_6
Q21
Q43
Q65
2-19
CE
D Q
CE
CE
CE
CE
CE
CE
CE
D Q
D Q
D Q
D Q
D Q
D Q
D Q
cdn
S1
S0
S2
S4
S6
S7
S5
S3
D Q
D Q
D Q
D Q
D Q
MachXO2 Family Data Sheet
D
D
D
T0
T2
T4
T6
T5
T3
T1
T7
Q0
Q2
Q4
Q6
Q7
Q5
Q3
Q1
SCLK
Architecture