a3pn010 Actel Corporation, a3pn010 Datasheet - Page 97

• Manufacturer Part Number: a3pn010
• Description: Proasic 3 Nano Flash Fpgas
• Manufacturer: Actel Corporation

Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be
driven and conditioned internally by the CCC module. For more details on clock conditioning
capabilities, refer to the
Table 2-131 on page 2-86
Minimum and maximum delays are measured with minimum and maximum loading.
Timing Characteristics
Table 2-128 • RT3PE600L Global Resource
Table 2-129 • RT3PE3000L Global Resource
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential
3. For specific junction temperature and voltage supply levels, refer to
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential
3. For specific junction temperature and voltage supply levels, refer to
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RMAX
RMAX
1.2 V DC Core Voltage
sequential element, located in a lightly loaded row (single element is connected to the global
net).
element, located in a fully loaded row (all available flip-flops are connected to the global net in
the row).
derating values.
sequential element, located in a lightly loaded row (single element is connected to the global
net).
element, located in a fully loaded row (all available flip-flops are connected to the global net in
the row).
derating values.
Input LOW Delay for Global Clock
Input HIGH Delay for Global Clock
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Input LOW Delay for Global Clock
Input HIGH Delay for Global Clock
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Military-Case Conditions: T
Military-Case Conditions: T
present minimum and maximum global clock delays within each device.
"Clock Conditioning Circuits" section on page
Description
Description
A dv a n c e v 0. 1
J
J
Radiation-Tolerant ProASIC3 DC and Switching Characteristics
= 125°C, V
= 125°C, V
CC
CC
= 1.14 V
= 1.14 V
Min.
Min.
1.80
1.79
1
1
–1
–1
Max.
Max.
2.06
2.09
0.30
Table 2-5 on page 2-8
Table 2-5 on page 2-8
2
2
2-87.
Min.
Min.
2.12
2.11
Std.
1
Std.
1
Table 2-128
Max.
Max.
2.42
2.45
0.35
2
2
Units
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2 - 85
for
for
to