a3pn010 Actel Corporation, a3pn010 Datasheet - Page 94

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a3pn010

Manufacturer Part Number
a3pn010
Description
Proasic 3 Nano Flash Fpgas
Manufacturer
Actel Corporation
Datasheet

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Radiation-Tolerant ProASIC3 FPGAs
Table 2-126 • Register Delays
2 -8 2
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
CLKQ
SUD
HD
SUE
HE
CLR2Q
PRE2Q
REMCLR
RECCLR
REMPRE
RECPRE
WCLR
WPRE
CKMPWH
CKMPWL
For specific junction temperature and voltage supply levels, refer to
values.
Timing Characteristics
Military-Case Conditions: T
Clock-to-Q of the Core Register
Data Setup Time for the Core Register
Data Hold Time for the Core Register
Enable Setup Time for the Core Register
Enable Hold Time for the Core Register
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width HIGH for the Core Register
Clock Minimum Pulse Width LOW for the Core Register
J
= 125°C, Worst-Case V
Description
A d v a n c e v 0. 1
CC
= 1.14 V
Table 2-5 on page 2-8
0.76
0.59
0.00
0.63
0.00
0.55
0.55
0.00
0.31
0.00
0.31
0.30
0.30
0.56
0.56
–1
0.90
0.70
0.00
0.74
0.00
0.65
0.65
0.00
0.36
0.00
0.36
0.34
0.34
0.64
0.64
Std.
for derating
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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