wm8352 Wolfson Microelectronics plc, wm8352 Datasheet - Page 250

• Manufacturer Part Number: wm8352
• Description: Wolfson Audioplus? Stereo Codec With Power Management
• Manufacturer: Wolfson Microelectronics plc

WM8352
REGISTER
Register 44h ADC Divider
REGISTER
Register 46h ADC LR Rate
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ADDRESS
ADC Divider
ADDRESS
REGISTER
Input Control
ADDRESS
R68 (44h)
R70 (46h)
R72 (48h)
ADC LR
Rate
BIT
BIT
10:0
11:8
BIT
7:4
2:0
11
3
10
9
8
2
ADCLRC_RATE[10:0] 000_0100_0000 Determines the number of bit clocks per LRC
ADCR_DAC_SVOL[3:0]
ADCL_DAC_SVOL[3:0]
IN1RN_ENA
IN1RP_ENA
ADC_CLKDIV[2:0]
ADCLRC_ENA
IN2R_ENA
IN2L_ENA
LABEL
ADCCLK_POL
LABEL
LABEL
DEFAULT
0
1
1
0
DEFAULT
DEFAULT
0000
0000
000
0
0
Connect IN2R pin to right channel input PGA
0 = IN2R not connected to input PGA amplifier
1 = IN2R connected to input PGA amplifier
Connect IN1RN pin to right channel input PGA
negative terminal.
0 = IN1RN not connected to input PGA
1 = IN1RN connected to right channel input PGA
amplifier negative terminal.
Connect IN1RP pin to right channel input PGA
amplifier positive terminal.
0 = IN1RP not connected to input PGA
1 = right channel input PGA amplifier positive terminal
connected to IN1RP (constant input impedance)
Connect IN2L pin to left channel input PGA amplifier
0 = IN2L not connected to input PGA amplifier
1 = IN2L connected to input PGA amplifier
Controls left digital side tone volume from -
36dB to 0dB in 3dB steps.
Controls right digital side tone volume from -
36dB to 0dB in 3dB steps.
ADC Clock Polarity
0 = Normal
1 = Inverted
ADC Sample rate divider
000 = SYSCLK / 1.0
001 = SYSCLK / 1.5
010 = SYSCLK / 2
011 = SYSCLK / 3
100 = SYSCLK / 4
101 = SYSCLK / 5.5
110 = SYSCLK / 6
111 = Reserved
Enables the LRC generation for the ADC
0 = disabled
1 = enabled
phase (when enabled)
00000000000 = invalid
...
00000000111 = invalid
00000001000 = 8 BCPS
…
11111111111 = 2047 BCPS
DESCRIPTION
DESCRIPTION
DESCRIPTION
PD, June 2009, Rev 4.1
REFER TO
REFER TO
REFER TO
Production Data
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