wm9712l Wolfson Microelectronics plc, wm9712l Datasheet - Page 67

• Manufacturer Part Number: wm9712l
• Description: Ac?97 Audio And Touchpanel Codec
• Manufacturer: Wolfson Microelectronics plc

Production Data
w
Note: PR6 to PR0 default to 1 if pin 47 is held high during reset, otherwise they default to 0.
28h
2Ah
2Ch
2Eh
32h
Note: The VRA bit in register 2Ah must be set first to obtain sample rates other than 48kHz
ADDR
ADDR
ADDR
ADDR
Register 26h is for power management according to the AC’97 specification. Note that the actual state of many circuit
blocks depends on both register 24h AND register 26h.
Register 28h is a read-only register that indicates to the driver which advanced AC’97 features the WM9712L supports.
Register 2Ah controls the SPDIF output and variable rate audio.
Registers 2Ch, 2Eh 32h and control the sample rates for the stereo DAC, auxiliary DAC and audio ADC, respectively.
REG
REG
REG
REG
14
13
12
11
10
9
8
3
2
1
0
15:14
11:10
9
8
7
6
3
2
1
0
10
5:4
2
0
all
all
all
BIT
BIT
BIT
BIT
PR6
PR5
PR4
PR3
PR2
PR1
PR0
REF
ANL
DAC
ADC
LABEL
ID
REV
AMAP
LDAC
SDAC
CDAC
VRM
SPDIF
DRA
VRA
SPCV
SPSA
SEN
VRA
DACSR
AUXDACSR
ADCSR
LABEL
LABEL
LABEL
inverse of PR2
inverse of PR3
inverse of PR1
inverse of PR0
see note
00
01
0
0
0
0
0
1
0
1
DEFAULT
DEFAULT
1 (valid)
01 (slots 6, 9)
0 (OFF)
0 (OFF)
BB80h
BB80h
BB80h
DEFAULT
DEFAULT
Indicates that the WM9712L is configured as the primary codec in
the system.
Indicates that the WM9712L conforms to AC’97 Rev2.2
Indicates that the WM9712L does not support slot mapping
Indicates that the WM9712L does not have an LFE DAC
Indicates that the WM9712L does not have Surround DACs
Indicates that the WM9712L does not have a Centre DAC
Indicates that the WM9712L does not have a dedicated, variable
rate microphone ADC
Indicates that the WM9712L supports SPDIF output
Indicates that the WM9712L does not support double rate audio
Indicates that the WM9712L supports variable rate audio
Disables HPOUTL, HPOUTR and OUT3 Buffer
Disables Internal Clock
Disables AC-link interface (external clock off)
Disables VREF, analogue mixers and outputs
Disables analogue mixers, LOUT2, ROUT2 (but not VREF)
Disables Stereo DAC and AUXDAC
Disables audio ADCs and input Mux
Read-only bit, Indicates VREF is ready
Read-only bit, indicates analogue mixers are ready
Read-only bit, indicates audio DACs are ready
Read-only bit, indicates audio ADCs are ready
SPDIF validity bit (read-only)
Controls SPDIF slot assignment. 00=slots 3 and 4,
01=6/9, 10=7/8, 11=10/11
Enables SPDIF output enable
Enables variable rate audio
Controls stereo DAC sample rate
Controls auxiliary DAC sample rate
Controls audio ADC sample rate
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
PD Rev 4.5 August 2006
WM9712L
Power
Management
Intel’s AC’97
Component
Specification,
Revision 2.2,
page 59
Digital Audio
(SPDIF)
Output
Variable Rate
Audio /
Sample Rate
Conversion
REFER TO
REFER TO
REFER TO
REFER TO
67