wm8961 Wolfson Microelectronics plc, wm8961 Datasheet - Page 81

• Manufacturer Part Number: wm8961
• Description: Ultra-low Power Stereo Codec With 1w Stereo Class D Speaker Drivers And Ground Referenced Headphone Drivers
• Manufacturer: Wolfson Microelectronics plc

REGISTER MAP
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The
WM8961 can be configured using the Control Interface. All registers not listed and all unused bits should not be written to.
All registers can be read back. Registers R1[15:12] returns the device ID when read.
w
R28 (1Ch)Anti-pop
R17 (11h) ALC1
R18 (12h) ALC2
R19 (13h) ALC3
R20 (14h) Noise Gate
R21 (15h) Left ADC
R22 (16h) Right ADC
R23 (17h) Additional
R24 (18h) Additional
R25 (19h) Pwr Mgmt (1)
R26 (1Ah) Pwr Mgmt (2)
R27 (1Bh) Additional
R30 (1Eh) Clocking 3
R32 (20h) ADCL signal
R33 (21h) ADCR signal
WM8961
R10 (Ah) Left DAC
R11 (Bh) Right DAC
R14 (Eh) Audio Interface
R15 (Fh) Software Reset
R0 (0h) Left Input
R1 (1h) Right Input
R2 (2h) LOUT1 volume
R3 (3h) ROUT1 volume
R4 (4h) Clocking1
R5 (5h) ADC & DAC
R6 (6h) ADC & DAC
R7 (7h) Audio Interface
R8 (8h) Clocking2
R9 (9h) Audio Interface
REG
volume
volume
Control 1
Control 2
0
1
volume
volume
2
volume
volume
control(1)
control(2)
Control (3)
path
NAME
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DEVICE_ID[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
11
CHIP_REV[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
10
0
0
0
0
0
0
0
0 ADC_HPF_CUT[1:0] DACPOL[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9
SW_RST_DEV_ID1[15:0]
ALCMODE
ALRSWAP BCLKINV MS DLRSWAP LRP
OUT1VU LO1ZC
OUT1VU RO1ZC
CLK_TO_DIV[1:0]
DACVU
DACVU
ADCVU
ADCVU
TSDEN
DACL
IPVU LINMUTE LIZC
IPVU RINMUTE RIZC
VMIDSEL[1:0]
ALCSEL[1:0]
0
0
0
0
0
0
0
0
0
8
DCLKDIV[2:0]
ADCDIV[2:0]
DACR LOUT1_PG
0
0
0
0
0
0
0
0
0
7
VREF
ADCPOL[1:0]
0
0
0
A
0
0
0
0
6
DCY[3:0]
MAXGAIN[2:0]
MINGAIN[2:0]
ROUT1_PG
CLK_SYS_
NGTH[4:0]
RMICBOOST[1:0]
LMICBOOST[1:0]
AINL
ENA
0
0
0
A
0
0 BUFDCOPE
LRCLK_RATE[8:0]
5
DACDIV[2:0]
CLK_DSP_
SPKL_PGA SPKR_PGA 0
DMONOMI
CLK_256K_DIV[5:0]
DACCOMP[1:0] ADCCOMP[1:0] LOOPBACK0000h
RDACVOL[7:0]
RADCVOL[7:0]
LDACVOL[7:0]
LADCVOL[7:0]
AINR
ENA
X
N
0
0
0
0
4
ROUT1VOL[6:0]
LOUT1VOL[6:0]
DACSMMDACMR DACSLOPE
BUFIOEN SOFT_ST
DACMU DEEMPH[1:0] ADCHPD 0008h
ADCL
TRIS
RINVOL[5:0]
LINVOL[5:0]
0
0
0
0
3
WL[1:0]
MCLKDIV
ADCR
BCLKDIV[3:0]
PP, August 2009, Rev 3.1
SAMPLE_RATE[2:0]
0
0
0
0
0
ALCL[3:0]
2
HLD[3:0]
ATK[3:0]
MICB
NGG
FORMAT[1:0]
0
0
0
0
0
0
0
1
MANUAL_M
DAC_OSR1
Pre-Production
NGAT
TOEN
ODE
28
0
0
0
0
0
0
0
0
DEFAULT
000Ah
00FFh
00FFh
007Bh
00C0h
00C0h
009Fh
029Fh
0000h
0000h
0020h
0000h
01F4h
0040h
1801h
0000h
0032h
0000h
0120h
0000h
0000h
0000h
0000h
0000h
005Fh
0000h
0000h
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