wm8961 Wolfson Microelectronics plc, wm8961 Datasheet - Page 78

• Manufacturer Part Number: wm8961
• Description: Ultra-low Power Stereo Codec With 1w Stereo Class D Speaker Drivers And Ground Referenced Headphone Drivers
• Manufacturer: Wolfson Microelectronics plc

VMID GENERATOR
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WM8961
Table 61 Volume Update Timeout Control
R30 (1Eh) Clocking 3
R23 (17h) Additional
REGISTER
ADDRESS
control(1)
BIT
8:7
0
CHARGE PUMP CLOCK
The Charge pump is driven from the SYSCLK plus a 4 kHz clock also generated from the SYSCLK,
and requires a minimum SYSCLK of 2.8224 MHz. The charge pump internal clock is derived from
SYSCLK, using a clock divider to generate a nominal 1MHz clock, as shown in Figure 43. The clock
divider ratio depends on the SAMPLE_RATE[2:0] and CLK_SYS_RATE[3:0] register settings.
For example, with MCLKDIV=0, SAMPLE_RATE[2:0]=000:
256fs: CLK_SYS_RATE[3:0]=0011 gives a charge pump clock division ratio of 12, hence
128fs: CLK_SYS_RATE[3:0]=0001 gives a charge pump clock division ratio of 6, hence
TIMEOUT CLOCK
The timeout clock triggers a volume update if a zero-cross has not been detected within the
configured time-frame. The timeout is enabled by TOEN and the timeout period is controlled by the
CLK_TO_DIV register as shown in Table 61
An internal VMID generator generates AVDD/2 as a reference voltage to be used as the virtual ground
for most internal analogue signal processing circuits. The internal VMID is output on the VMID pin.
This pin requires a 4.7uF filtering capacitor.
VMIDSEL is the enable for the VMID reference, which defaults to disabled. VMIDSEL allows the
charging and discharging of the external VMID capacitor to be controlled. It is recommended that the
user use the fast start-up mode (VMIDSEL=11) when VMID is initially enabled. Then the user should
switch to a lower power operating mode (VMIDSEL=01) for normal operation.
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CLK_TO_DIV[1:0]
MCLK=12.288MHz gives a charge pump frequency of 1.024MHz at full output power.
MCLK=11.2896MHz gives a charge pump frequency of 940.8kHz at full output power.
MCLK=6.144MHz gives a charge pump frequency of 1.024MHz at full output power.
MCLK=5.6448MHz gives a charge pump frequency of 940.8kHz at full output power
Fast Start Up: use10k Ω divider
Normal Mode: use 100k Ω divider
Standby: use 500k Ω divider
LABEL
TOEN
DEFAULT
00
0
Timeout/slow clock divider setting
00 : 125Hz ( timeout = 8ms)
01 : 250Hz ( timeout = 4ms)
10 : 500Hz ( timeout = 2ms)
11 : 1kHz ( timeout = 1ms)
Slow clock enable for volume update timeout
DESCRIPTION
PP, August 2009, Rev 3.1
Pre-Production
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