73m2921 ETC-unknow, 73m2921 Datasheet - Page 9

• Manufacturer Part Number: 73m2921
• Description: Advanced Single Chip Modem
• Manufacturer: ETC-unknow

REGISTER NAME:
For a clean DSPCK transition when stopping the DSP (
oscillator (ENOSC) being disabled.
For a clean DSPCK transition when starting the DSP (
oscillator (ENOSC) is enabled. This happens automatically after reset or power up.
February 99 Rev M
D15
BIT NO.
D1, D2
D10,
D13,
D14,
DSPCK (2:0)
D12
D11
D15
D4,
D5,
D9,
D0
D3
D6
D7
D8
D14
Power Up
Source
Disable[1,0]
Reset Chip
Main Timer
Clock Divisor
Enable
Oscillator
Enable Micro-
processor
Clock
Microcontroller
Clock Divisor
Enable DSP
Clock
DSP Clock
D13
NAME
DSPCK
D12
EN
CR0
D11
D11 D10 D9
D15 D14 D13
MCLK (2:0)
CONDITION
D6
1
1
0
D10
1
0
D5
1
0
1
0
1
0
1
1
1
ADDRESS: UA00, 01h
D9
D4
1
1
1
MCLK
TDK Semiconductor
EN
D8
DESCRIPTION
Set to a logic 1 by the RESET pin, the RESET CHIP bit, or
by powering up the chip. To enable the DSP, the
bit must be high.
Causes a RESET interrupt to be continuously held for the
DSP. While low, the DSP will remain at instruction location
0x0000.
Used to mask the external power up source pins,
A logical 1 on PSDIS[1] masks
PSDIS[0] masks
Resets the state of the 73M2921 putting it into a known
state. The function of this bit is similar to that of the RESET
pin, except that this bit does NOT change the setting of the
POWERUP SOURCE DISABLE bits. See Table 2.
Must be set to provide 4.608MHz to the timer.
values
18.432 MHz oscillator frequency.
Enables the master oscillator. (Must be set to run)
Disables the oscillator and stops all chip activity.
For a clean MICCLK transition when stopping the clock (EN
MCLK=0), the EN MCLK bit must be turned off prior to the
oscillator (EN OSC) being disabled.
MICCLK enabled.
MICCLK disabled (Set to 0 if not using MICCLK).
Controls the frequency of the MICCLK output as a function
of the oscillator frequency. Default values shown should be
used with the 18.432 oscillator frequency. Set these to 0 if
not using MICCLK (See Table 3).
Set by the RESET pin, the RESET CHIP bit, or by powering
up the chip.
DSP clock enabled. (Must be set to run)
DSP clock disabled.
Controls the internal DSP clock frequency as a function of the
oscillator frequency. Default values shown should be used with
the 18.432 MHz oscillator frequency.
.
OSC
D7
EN
shown
D6
=0), the
=1), the
MAINCK (2:0)
D5
(WRITE ONLY)
should
.
D4
RESET
bit must be set low prior to the
bit must be set high after the
be
Advanced Single
D3
used
Chip Modem
.
D2
PSDIS
(1:0)
A logical 1 on
73M2921
D1
with
Page 9 of 41
Default
D0
and
the