73m2921 ETC-unknow, 73m2921 Datasheet - Page 24

• Manufacturer Part Number: 73m2921
• Description: Advanced Single Chip Modem
• Manufacturer: ETC-unknow

DETECT REGISTER 1 (READ ONLY)
73M2921
Advanced Single
Chip Modem
DETECT 1 ENABLE REGISTER
This is the enable register for Detect 1. Setting bits TO 1 in this register enables the unsolicited interrupt feature.
These bits have a 1 to 1 correspondence with Detect Register 1. The default value is “0”. See Detect Register 1.
Page 24 of 41
BIT D7
BIT D7
BIT NO.
CAS
CAS
D0
D1
D2
D3
D4
D5
D6
D7
Energy Detect
Carrier Detect
Handshake in
BIT D6
CAS Tone
BIT D6
Reserved
Reserved
S1 Detect
progress
RDLBD
NAME
Detect
S1
S1
BIT D5
BIT D5
Valid in call Progress
RES
RES
Valid in Data Mode
Valid in Data Mode
Valid in Data Mode
Valid in Data Mode
Valid in All Modes
CONDITION
Mode
ADDRESS: 08h (08d, 01000b)
ADDRESS: 09h (09d, 01001b)
BIT D4
BIT D4
EGY
EGY
TDK Semiconductor
DESCRIPTION
Reserved.
RDLB Detect
This bit will be set when conditions for V.24 circuit 104
are met by the modulation mode being used (Modem in
data mode).
This bit will be set if a handshake is currently in progress.
This bit is cleared by the 73M2921 when either a
handshake has been successful and the 73M2921 has
entered DATA mode, or when a handshake has been
aborted and the 73M2921 is placed into IDLE mode.
This bit will be set if receive level is above a
predetermined threshold.
Reserved.
This bit will be set if S1 (Unscrambled 1100 @ 1200b/s)
is detected. This bit is also used to detect a Retrain
request if connected V.22bis or V.22 and S1 is detected.
This bit will be set if the CAS tone (2130Hz + 2750 Hz) is
detected.
BIT D3
BIT D3
HIP
HIP
BIT D2
BIT D2
CAR
CAR
MODE: SEE DET REG 1
RDLBD
BIT D1
RDLBD
BIT D1
MODE: SEE BELOW
February 99 Rev M
BIT D0
BIT D0
RES
RES