sc16c750-04 NXP Semiconductors, sc16c750-04 Datasheet - Page 6

• Manufacturer Part Number: sc16c750-04
• Description: Sc16c750 Universal Asynchronous Receiver/transmitter Uart With 64-byte Fifo
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 2:
9397 750 11623
Product data
Symbol
CS0, CS1,
CS2
CTS
D7-D0
DCD
DDIS
DSR
DTR
INT
MR
NC
Pin description
Pin
PLCC44 LQFP64
14, 15,
16
40
2-9
42
26
41
37
33
39
34
59, 61, 62
33
52, 51, 50,
48, 46, 45,
43, 42
36
12
35
28
23
32
3, 5, 7, 11,
14, 16, 19,
22, 24, 27,
29, 31, 34,
37, 39, 41,
44, 47, 49,
53, 56, 57,
60, 63
…continued
Type
I
I
I/O
I
O
I
O
O
I
Description
Chip select. When CS0 and CS1 are HIGH and CS2 is LOW, these three
inputs select the UART. When any of these inputs are inactive, the UART
remains inactive (refer to AS description).
Clear to send. CTS is a modem status signal. Its condition can be checked
by reading bit 4 (CTS) of the modem status register. Bit 0 ( CTS) of the
modem status register indicates that CTS has changed states since the last
read from the modem status register. If the modem status interrupt is
enabled when CTS changes levels and the auto-CTS mode is not enabled,
an interrupt is generated. CTS is also used in the auto-CTS mode to control
the transmitter.
Data bus. Eight data lines with 3-State outputs provide a bi-directional path
for data, control and status information between the UART and the CPU.
Data carrier detect. DCD is a modem status signal. Its condition can be
checked by reading bit 7 (DCD) of the modem status register. Bit 3 ( DCD)
of the modem status register indicates that DCD has changed states since
the last read from the modem status register. If the modem status interrupt
is enabled when DCD changes levels, an interrupt is generated.
Driver disable. DDIS is active (LOW) when the CPU is not reading data.
When active, DDIS can disable an external transceiver.
Data set ready. DSR is a modem status signal. Its condition can be
checked by reading bit 5 (DSR) of the modem status register. Bit 1 ( DSR)
of the modem status register indicates DSR has changed levels since the
last read from the modem status register. If the modem status interrupt is
enabled when DSR changes levels, an interrupt is generated.
Data terminal ready. When active (LOW), DTR informs a modem or data
set that the UART is ready to establish communication. DTR is placed in the
active level by setting the DTR bit of the modem control register. DTR is
placed in the inactive level either as a result of a Master Reset, during loop
mode operation, or clearing the DTR bit.
Interrupt. When active (HIGH), INT informs the CPU that the UART has an
interrupt to be serviced. Four conditions that cause an interrupt to be issued
are: a receiver error, received data that is available or timed out (FIFO mode
only), an empty transmitter holding register or an enabled modem status
interrupt. INT is reset (deactivated) either when the interrupt is serviced or
as a result of a Master Reset.
Master Reset. When active (HIGH), MR clears most UART registers and
sets the levels of various output signals.
Not connected.
Rev. 04 — 20 June 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
UART with 64-byte FIFO
SC16C750
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