sc16c652 NXP Semiconductors, sc16c652 Datasheet - Page 19
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sc16c652
Manufacturer Part Number
sc16c652
Description
Dual Uart With 32 Bytes Of Transmit And Receive Fifos
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C652.pdf
(41 pages)
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Product data
Table 11:
Table 12:
Table 13:
Bit
1
0
FCR[7]
0
0
1
1
FCR[5]
0
0
1
1
Symbol
FCR[1]
FCR[0]
FIFO Control Register bits description
RCVR trigger levels
TX FIFO trigger levels
FCR[6]
0
1
0
1
FCR[4]
0
1
0
1
Rev. 04 — 20 June 2003
Description
RCVR FIFO reset.
FIFO enable.
Logic 0 = No FIFO receive reset (normal default condition).
Logic 1 = Clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
Logic 0 = Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO. This bit must be a
‘1’ when other FCR bits are written to, or they will not be
programmed.
Dual UART with 32 bytes of transmit and receive FIFOs
RX FIFO trigger level (bytes)
8
16
24
28
TX FIFO trigger level (bytes)
16
8
24
30
…continued
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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