sc16c652 NXP Semiconductors, sc16c652 Datasheet
sc16c652
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sc16c652 Summary of contents
Page 1
... An internal loop-back capability allows on-board diagnostics. Independent programmable baud rate generators are provided to select transmit and receive baud rates. The SC16C652 operates 3.3 V and 2.5 V and the Industrial temperature range, and is available in a plastic LQFP48 package. 2. Features 2 channel UART ...
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... Dual UART with 32 bytes of transmit and receive FIFOs 5-, 6-, 7-, or 8-bit characters Even-, Odd-, or No-Parity formats 1 1 2-stop bit 2 Baud generation ( Mbit/s) Loop-back controls for communications link fault isolation Rev. 04 — 20 June 2003 SC16C652 Version 7 1.4 mm SOT313-2 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... A0–A2 REGISTER CSA SELECT CSB LOGIC INTA, INTB INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB LOGIC Fig 1. SC16C652 block diagram. 9397 750 11634 Product data Dual UART with 32 bytes of transmit and receive FIFOs TRANSMIT TRANSMIT FIFO SHIFT REGISTER REGISTER RECEIVE RECEIVE FIFO ...
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... I Chip Select A, B (Active-LOW). This function is associated with individual channels, A through B. These pins enable data transfers between the user CPU and the SC16C652 for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing a logic 0 on the respective CSA, CSB pin. ...
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... IOR 19 I Read strobe (Active-LOW strobe). A logic 0 transition on this pin will load the contents of an internal register defined by address bits A0-A2 onto the SC16C652 data bus (D0-D7) for access by external CPU. IOW 15 I Write strobe (Active-LOW strobe). A logic 0 transition on this pin will transfer the contents of the data bus (D0-D7) from the external CPU to an internal register that is defi ...
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... O Transmit data A, B. These outputs are associated with individual serial transmit channel data from the SC16C652. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the TX output pin is disabled and TX data is internally connected to the UART RX input. ...
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... The FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The SC16C652 is capable of operation Mbits/s with a 24 MHz clock. With a crystal or external clock input of 7.3728 MHz, the user can select data rates up to 460.8 kbits/s. ...
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... Philips Semiconductors 6.2 Internal registers The SC16C652 provides two sets of internal registers (A and B) consisting of 12 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user accessible scratchpad register (SPR) ...
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... Following a suspension due to a match of the Xoff characters’ values, the SC16C652 will monitor the receive data stream for a match to the Xon1,2 character value(s match is found, the SC16C652 will resume operation and clear the flags (ISR[4]). Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. ...
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... In the event that the receive buffer is overfilling and flow control needs to be executed, the SC16C652 automatically sends an Xoff message (when enabled) via the serial TX output to the remote modem. The SC16C652 sends the Xoff1,2 characters as soon as received data passes the programmed trigger level. To clear this condition, the SC16C652 will transmit the programmed Xon1,2 characters as soon as receive data drops below the programmed trigger level ...
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... TX/RX channel control. The programmable Baud Rate Generator is capable of operating with a frequency MHz. To obtain maximum data rate necessary to use full rail swing on the clock input. The SC16C652 can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins ...
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... DMA operation The SC16C652 FIFO trigger level provides additional flexibility to the user for block mode operation. The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY output pins ...
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... FIFO SHIFT REGISTER REGISTER MODEM CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 Rev. 04 — 20 June 2003 SC16C652 TXA, TXB MCR[ RXA, RXB RTSA, RTSB CTSA, CTSB DTRA, DTRB DSRA, DSRB (OP1A, OP1B) RIA, RIB (OP2A, OP2B) CDA, CDB 002aaa350 © ...
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... Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BF 9397 750 11634 Product data Dual UART with 32 bytes of transmit and receive FIFOs details the assigned bit functions for the SC16C652 internal registers. The Bit 7 Bit 6 Bit 5 Bit 4 ...
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... The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a Receive Serial Shift Register (RSR). Receive data is removed from the SC16C652 and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16 clock rate ...
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... FIFO drops below the trigger level. Logic 0 = Disable the receiver ready (ISR level 2, RXRDY) interrupt (normal default condition). Logic 1 = Enable the RXRDY (ISR level 2) interrupt. Rev. 04 — 20 June 2003 SC16C652 …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Philips Semiconductors 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C652 in the FIFO polled mode of operation. In this mode, interrupts are not generated and the user must poll the LSR register for TX and/or RX data status. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s) ...
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... FIFO is completely full. It will be a logic 0 when the trigger level has been reached. Receive operation in mode ‘1’: When the SC16C652 is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached Receive Time-Out has occurred, the RXRDY pin will logic 0 ...
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... FCR bits are written to, or they will not be programmed. RCVR trigger levels FCR[6] RX FIFO trigger level (bytes FIFO trigger levels FCR[4] TX FIFO trigger level (bytes Rev. 04 — 20 June 2003 SC16C652 …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Philips Semiconductors 7.4 Interrupt Status Register (ISR) The SC16C652 provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... LCR[2] stop bit length Word length Stop bit length (bit times LCR[1-0] word length LCR[0] Word length Rev. 04 — 20 June 2003 SC16C652 Table 17). Table 18). Table 19). © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Logic 1 = Forces the INT (A-B outputs to the active mode and sets OP2 to a logic 0. MCR[2] (OP1). OP1A/OP1B are not available as an external signal in the SC16C652. This bit is instead used in the Loop-back mode only. In the loop-back mode, this bit is used to write the state of the modem RI interface signal. MCR[1] RTS Logic 0 = Force RTS output to a logic 1 (normal default condition) ...
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... Philips Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C652 and the CPU. Table 21: Bit 9397 750 11634 Product data Dual UART with 32 bytes of transmit and receive FIFOs Line Status Register bits description ...
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... Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C652 is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state. These bits are set to a logic 0 whenever the CPU reads this register ...
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... Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated. 7.9 Scratchpad Register (SPR) The SC16C652 provides a temporary data register to store 8 bits of user information. 7.10 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bits 0 through 4 provide single or dual character software flow control selection. ...
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... SC16C554 mode. (Normal default condition.) Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1, all enhanced features of the SC16C652 are enabled and user settings stored during a reset will be restored. EFR[3-0] Cont-3-0 Tx, Rx control. Logic 0 or cleared is the default condition. ...
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... Philips Semiconductors 7.11 SC16C652 external reset condition Table 25: Register IER FCR ISR LCR MCR LSR MSR SPR DLL DLM Table 26: Output TXA, TXB OP2A, OP2B RTSA, RTSB DTRA, DTRB INTA, INTB 8. Limiting values Table 27: In accordance with the Absolute Maximum Rating System (IEC 60134). ...
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... 0.4 OL (databus 1 0.4 OL (other outputs (databus (other outputs 800 A 1. (data bus 400 A 1. (other outputs MHz - 3 Rev. 04 — 20 June 2003 SC16C652 3.3 V 5.0 V Unit Min Max Min Max 0.3 0.6 0.5 0.6 V 2 0.3 0.8 0.5 0.8 V 2 ...
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... Rev. 04 — 20 June 2003 SC16C652 3.3 V 5.0 V Unit Max Min Max - MHz - ...
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... Dual UART with 32 bytes of transmit and receive FIFOs t 6h VALID ADDRESS t 13h ACTIVE t 15d t 13w ACTIVE t 16h t 16s DATA t 6h VALID ADDRESS t 7h ACTIVE ACTIVE t 12h t 12d DATA Rev. 04 — 20 June 2003 SC16C652 002aaa109 002aaa110 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Dual UART with 32 bytes of transmit and receive FIFOs t 17d CHANGE OF STATE CHANGE OF STATE t 18d ACTIVE t 19d ACTIVE Rev. 04 — 20 June 2003 SC16C652 CHANGE OF STATE t 18d ACTIVE ACTIVE ACTIVE ACTIVE t 18d CHANGE OF STATE 002aaa352 002aaa112 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS 16 BAUD RATE CLOCK DATA BITS (5– Rev. 04 — 20 June 2003 SC16C652 NEXT DATA PARITY STOP START BIT BIT BIT 20d ACTIVE t 21d ACTIVE 002aaa113 NEXT DATA ...
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... D4 D5 DATA BITS (5– DATA BITS 6 DATA BITS 7 DATA BITS ACTIVE TX READY t 22d 16 BAUD RATE CLOCK Rev. 04 — 20 June 2003 SC16C652 PARITY STOP BIT BIT D6 D7 FIRST BYTE THAT REACHES THE TRIGGER LEVEL t 25d ACTIVE DATA READY t 26d ...
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... Dual UART with 32 bytes of transmit and receive FIFOs DATA BITS (5- ACTIVE TRANSMITTER READY NOT READY Rev. 04 — 20 June 2003 SC16C652 NEXT DATA PARITY STOP START BIT BIT BIT D6 D7 002aaa117 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Dual UART with 32 bytes of transmit and receive FIFOs DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS t 28d FIFO FULL Rev. 04 — 20 June 2003 SC16C652 PARITY STOP BIT BIT D6 D7 002aaa365 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... 2 scale (1) ( 0.18 7.1 7.1 9.15 9.15 0.5 1 0.12 6.9 6.9 8.85 8.85 REFERENCES JEDEC JEITA MS-026 Rev. 04 — 20 June 2003 SC16C652 SOT313 detail X (1) ( 0.75 0.95 0.95 7 0.2 0.12 0.1 o 0.45 0.55 0.55 0 EUROPEAN ISSUE DATE PROJECTION 00-01-19 03-02-25 © ...
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... Product data Dual UART with 32 bytes of transmit and receive FIFOs 2 called small/thin packages. Rev. 04 — 20 June 2003 SC16C652 3 350 mm so called © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Product data Dual UART with 32 bytes of transmit and receive FIFOs Suitability of surface mount IC packages for wave and reflow soldering methods [1] [ SO, SOJ Rev. 04 — 20 June 2003 SC16C652 Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable ...
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... Product data (9397 750 10335); ECN 853-2382 28948 of 16 September 2002. 9397 750 11634 Product data Dual UART with 32 bytes of transmit and receive FIFOs 10 C measured in the atmosphere of the reflow 11: changed capacitors’ values and Rev. 04 — 20 June 2003 SC16C652 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Rev. 04 — 20 June 2003 SC16C652 Fax: + 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Scratchpad Register (SPR 7.10 Enhanced Feature Register (EFR 7.11 SC16C652 external reset condition . . . . . . . . 27 © Koninklijke Philips Electronics N.V. 2003. Printed in the U.S.A All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice ...