xr88c681 Exar Corporation, xr88c681 Datasheet - Page 78

• Manufacturer Part Number: xr88c681
• Description: Cmos Dual Channel Uart Duart
• Manufacturer: Exar Corporation

this bit is set for a given character, it will be cleared if the
STOP bit is properly detected in the next character.
If the “Error” Mode has been set to “Block” mode, then this
bit, once set will remain asserted until the “RESET
ERROR STATUS” command has been invoked (please
see Table 3). Please note that if the Error Mode is “Block”
this bit, in the Status Register will remain set, for all
subsequent characters, independent of the condition of
these received characters, until the “RESET ERROR
STATUS” command has been invoked.
SRn[5] Parity Error
This bit is set when the “WITH PARITY” or “FORCE
PARITY”
corresponding character in the data FIFO was received
with incorrect parity.
If the Error Mode has been set to “Character” Mode, this
bit only applies to the Character at the top of the RHR. If
this bit is set for a given character, it will be cleared if the
received parity is correct in the next character.
If the “Error” Mode has been set to “Block” mode, then this
bit, once set will remain asserted until the “RESET
ERROR STATUS” command has been invoked (please
see Table 3). Please note that if the Error Mode is “Block”
this bit, in the Status Register will remain set, for all
subsequent characters, independent of the condition of
these received characters, until the “RESET ERROR
STATUS” command has been invoked.
SRn[4] Overrun Error
If set, this bit indicates that one or more characters in the
received data have been lost, it is set upon receipt of a
new character when the FIFO is full and a character is
already in the RSR waiting for an empty FIFO position.
When this occurs, the character in the RSR is overwritten.
Please note that unlike the Status Register bits for FE
(Framing Error), PE (Parity Error) and RB (Received
Break), the OE (Overrun Error) indicator is always flagged
on a “Block” Error Mode basis. The OE condition is never
flagged on a character-to-character basis, and only
cleared when the “RESET ERROR STATUS” command is
invoked.
Rev. 2.11
modes
are
programmed
and
if
the
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SRn[3] Transmitter Empty (TXEMT)
This bit is set when the transmitter underruns. It is set
after transmission of the last stop bit of a character and if
there is no character in the THR or TSR awaiting
transmission. This bit is cleared when the transmitter is
disabled, or when the CPU writes a new character to the
THR.
SRn[2] Transmitter Ready (TXRDY)
This bit, when set, indicates that the THR is empty and
ready to accept a character from the CPU. The bit is
cleared when the CPU writes a new character to the THR,
and is set when that character is transferred to the TSR.
TXRDY is set when the transmitter is initially enabled and
is reset when the transmitter is disabled. Characters
loaded into the THR while the transmitter is disabled will
not be transmitted.
SRn[1] FIFO Full (FFULL)
This bit is set when a character is transferred from the
RSR to the RHR and the transfer causes it to become full,
i.e., all three FIFO positions are occupied. It is reset when
the CPU reads the RHR. If a character is waiting in the
RSR because the FIFO is full, FFULL will not be reset
when the CPU reads the RHR.
SRn[0] Receiver Ready (RXRDY)
This bit indicates that at least one character has been
received and is waiting in the FIFO to be read by the CPU.
It is set when a character is transferred from the RSR to
the RHR and is cleared with the CPU reads the last
character currently stored in the FIFO.
Please note that some of the conditions that are flagged
by the Status Register can also be programmed to
generate an Interrupt Request to the CPU. However,
there are some conditions that are flagged by the Status
Register that cannot be programmed to generate an
Interrupt. These conditions are listed here:
D SRn[6] - Framing Error
D SRn[5] - Parity Error
D SRn[4] - Overrun Error
Therefore, if system level error-checking is not employed,
the user is recommended to validate each character by
checking the Status Register.