xr88c681 Exar Corporation, xr88c681 Datasheet - Page 5

• Manufacturer Part Number: xr88c681
• Description: Cmos Dual Channel Uart Duart
• Manufacturer: Exar Corporation

44 PLCC
Rev. 2.11
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
40 PDIP,
CDIP
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28 PDIP
10
12
13
14
15
16
17
18
19
11
9
(RXCB_1X)
(-C/T_RDY)
(TXRDY_B)
(TXCB_1X)
-FFULL_B)
(-TXRDY_A)
(-RXRDY/
(-RTSB)
Symbol
-
GND
OP1
OP3
OP5
OP7
INTR
OP6
NC
D1
D3
D5
D7
D6
D4
D2
D0
PWR
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
5
Description
Output 1 (General Purpose Output). This output can also
be programmed to function as the active-low, “Channel B
Request-to-Send” Output (-RTSB).
Output 3 (General Purpose Output). This output port can
also be programmed to function as: the “Channel B Trans-
mitter 1X clock” output (TXCB_1X), the “Channel B Receiv-
er 1X clock” output (RXCB_1X), or the open drain, active-
low “Counter/Timer Ready” output (-C/T_RDY).
Output 5 (General Purpose Output Pin). This output port
pin can also be programmed to function as the open-drain,
active-low, Channel B “Receive Ready” or “Receiver FIFO
Full” indicator output (-RXRDY_B/-FFULL_B).
Output 7. (General Purpose Output Pin). This output port
pin can also be programmed to function as the open-drain,
active-low, “Transmitter Ready” indicator output for Channel
B (
Bi-Directional Data Bus.
Bi-Directional Data Bus.
Bi-Directional Data Bus.
MSB of the Eight Bit Bi-Directional Data Bus. All transfers
between the CPU and the DUART take place over this bus
(consisting of pins D0 - D7). The bus is tri-stated when the
-
Mode).
Signal Ground.
No Connect.
Interrupt Request Output (Active Low, Open Drain).
-
chip’s maskable interrupting conditions. This signal will re-
main asserted throughout the Interrupt Service Routine and
will be negated once the condition(s) causing the Interrupt
Request has been eliminated.
Bi-Directional Data Bus.
Bi-Directional Data Bus.
Bi-Directional Data Bus.
LSB of the Eight Bit Bi-Directional Data Bus. All transfers
between the CPU and the DUART take place over this bus.
The bus is tri-stated when the
during an IACK cycle (in the Z-Mode).
Output 6 (General Purpose Output). This output pin can
also be programmed to function as the open drain, active-
low, “Transmitter Ready” indicator output for Channel A
(
CS input is “high”, except during an IACK cycle (in the Z-
INTR is asserted upon the occurrence of one or more of the
-
TXRDY_A).
-
TXRDY_B).
-
CS input is “high”, except
XR88C681