xr16l784iv Exar Corporation, xr16l784iv Datasheet - Page 23
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xr16l784iv
Manufacturer Part Number
xr16l784iv
Description
High Performance 2.97v To 5.5v Quad Uart
Manufacturer
Exar Corporation
Datasheet
1.XR16L784IV.pdf
(52 pages)
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xr
REV. 1.2.2
TIMER [7:0] (default 0x00): Reserved.
TIMERMSB [7:0] and TIMERLSB [7:0]
TIMERMSB and TIMERLSB form a 16-bit value. The least-significant bit of the timer is being bit [0] of the
TIMERLSB with most-significant-bit being bit [7] in TIMERMSB. Reading the TIMERCNTL register will clear its
interrupt. Default value is zero upon powerup and reset.
Each bit selects 8X or 16X sampling rate for that UART channel, bit-0 is channel 0. Logic 0 (default) selects
normal 16X sampling with logic one selects 8X sampling rate. Transmit and receive data rates will double by
selecting 8X.
The 8-bit Reset register [RESET] provides the software with the ability to reset individual UART(s) when there
is a need. Each bit is self-resetting after it is written a logic 1 to perform a reset to that channel. All registers in
that channel will be reset to the default condition, see
UART channel 0 with bit-3=1 resets channel 3.
3.1.3
3.1.4
3.1.5
Bit-15
8XMODE [7:0] (default 0x00)
REGA [7:0] reserved
RESET [7:0] (default 0x00)
Bit-14
Bit-13
TIMERMSB Register
Bit-12
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2
Rsvd
Bit-11
16-Bit Timer/Counter Programmable Registers
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Rsvd
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Individual UART Channel 8X Clock Mode Enable
Rsvd
(default 0x00)
Rsvd
Bit-10
Individual UART Channel Reset Enable
Rsvd
Rsvd
Rsvd
TIMERCNTL Register
Bit-9
Rsvd Rsvd Ch-3 Ch-2 Ch-1 Ch-0
Rsvd Rsvd Ch-3 Ch-2 Ch-1 Ch-0
8XMODE Register
RESET Register
Rsvd
Bit-8
23
Select
Clock
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
Table 19
Bit-7
Re-trigger
Single/
Bit-6
for details. As an example, bit-0 =1 resets
Bit-1 Bit-0
Start/
Stop
Bit-5
TIMERLSB Register
Enable
Bit-4
INT
Bit-3
Bit-2
Bit-1
XR16L784
Bit-0