xr16l784iv Exar Corporation, xr16l784iv Datasheet
xr16l784iv
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xr16l784iv Summary of contents
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OCTOBER 2005 GENERAL DESCRIPTION 1 The XR16L784 (784 Asynchronous Receiver and Transmitter (UART). The device is designed for high bandwidth requirement in communication systems. The global interrupt source register provides a complete indication for all 4 channels ...
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... SSIGNMENT 48 XTAL2 XTAL1 GND VCC TX0 DTR0# RTS0# RI0# CD0# DSR0# CTS0# RX0 INT# CS ORDERING INFORMATION ART UMBER XR16L784CV 64-Lead LQFP XR16L784IV 64-Lead LQFP XR16L784 64-LQFP ...
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REV. 1.2.2 PIN DESCRIPTIONS Pin Descriptions AME IN DATA BUS INTERFACE A7-A0 6-1,64,63 D7:D0 18-11 IOR# 7 IOW# 8 (R/W#) CS# 62 INT MODEM OR SERIAL I/O INTERFACE TX0 53 RX0 60 RTS0# ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART Pin Descriptions AME IN DTR0# 54 DSR0# 58 CD0# 57 RI0# 56 TX1 48 RX1 41 RTS1# 46 CTS1# 42 DTR1# 47 DSR1# 43 CD1# 44 RI1# 45 ...
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REV. 1.2.2 Pin Descriptions AME IN TX3 28 RX3 21 RTS3# 26 CTS3# 22 DTR3# 27 DSR3# 23 CD3# 24 RI3# 25 ANCILLARY SIGNALS XTAL1 50 XTAL2 49 TMRCK 31 ENIR 32 RST# 20 16/68# ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART 1.0 DESCRIPTION The XR16L784 (784) integrates the functions of 4 enhanced 16550 UARTs, a general purpose 16-bit timer/ counter and an on-chip oscillator. The device configuration registers include a set of four ...
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REV. 1.2.2 2.4 INT# Ouput The INT# interrupt output changes according to the operating mode and enhanced features setup. and 3 summarize the operating behavior for the transmitter and receiver. T ABLE Auto RS485 Mode INT# Pin NO HIGH ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART 2.6 Programmable Baud Rate Generator A single Baud Rate Generator (BRG) is provided for the transmitter and receiver, allowing independent TX/RX channel control. The programmable Baud Rate Generator is capable of operating ...
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REV. 1.2.2 Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the operating data rate. Table 4 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X clock ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART IGURE RANSMITTER PERATION IN NON Data Byte 16X or 8X Clock 2.7.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with ...
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REV. 1.2.2 2.8.1 Receive Holding Register (RHR) - Read-Only The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data interface to the host processor. The ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART 2.9 THR and RHR Register Locations The THR and RHR register addresses for channel 0 to channel 7 is shown in RHR for channels are located at address 0x00, ...
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REV. 1.2.2 2.10.1 Auto CTS/DSR Flow Control Automatic CTS/DSR flow control is used to prevent data overrun to the remote receiver FIFO. The CTS/DSR pin is monitored to suspend/restart local transmitter. The flow control features are individually selected to ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART 2.11 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the 784 will ...
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REV. 1.2.2 2.13 Auto RS485 Half-duplex Control The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR bit-5. It asserts RTS# or DTR# (LOW) after a specified delay indicated in MSR[7:4] following the ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART F 11 IGURE NFRARED TX Data Transmit IR Pulse (TX Pin) Receive IR Pulse (RX pin) RX Data RANSMIT ATA NCODING AND ECEIVE Character Data Bits 1 ...
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REV. 1.2.2 2.15 Sleep Mode with Wake-Up Indicator The 784 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. All of these conditions must be ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART 2.16 Internal Loopback Each UART channel provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART ...
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REV. 1.2.2 3.0 XR16L784 REGISTERS The XR16L784 quad UART register set consists of the Device Configuration Registers that are accessible directly from the data bus for programming general operating conditions of the UARTs and monitoring the status of various ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART DDRESS EAD EGISTER IT [A7:A0] W RITE 0x80 R INT0 Rsvd Source UART 2 0x81 R INT1 bit 1 0x82 R INT2 Rsvd 0x83 R ...
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REV. 1.2.2 3.1.1 The Global Interrupt Source Registers The XR16L784 has a global interrupt source register set that consists of 4 consecutive registers [INT0, INT1, INT2 and INT3]. Register INT3 is not used in the 784 UART, only in ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART T 9: UART C ABLE RIORITY None RXRDY & RX Line Status (logic OR ...
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REV. 1.2.2 Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Rsvd TIMER [7:0] (default 0x00): Reserved. TIMERMSB [7:0] and TIMERLSB [7:0] TIMERMSB and TIMERLSB form a 16-bit value. The least-significant bit of the timer is being bit [0] of the TIMERLSB ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART 3.1.6 SLEEP [7:0] - (default 0x00) The 8-bit Sleep register enables each UART separately to enter Sleep mode. Sleep mode reduces power consumption when the system needs to put the UART(s) to ...
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REV. 1.2.2 3.2 UART CHANNEL CONFIGURATION REGISTERS The first 8 registers are 16550 compatible with EXAR enhanced feature registers located on the upper 8 addresses. The 4 sets of UART configuration registers are decoded using address lines A0 to ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART T 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A3- AME RITE RHR R Bit ...
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REV. 1.2.2 T 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A3- AME RITE RXCNT R Bit RXTRG W Bit-7 ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART IER[0]: RHR Interrupt Enable The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when the receive FIFO has reached the programmed trigger ...
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REV. 1.2.2 4.4.1 Interrupt Generation: • LSR is by any of the LSR bits and 4. • RXRDY trigger level. • RXRDY Time-out 4-char plus 12 bits delay timer. • ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART ISR[7:6]: FIFO Enable Status These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are enabled. 4.5 FIFO Control ...
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REV. 1.2.2 T 14: T ABLE RANSMIT AND T FCTR FCTR FCR RIGGER ABLE Table Table Table-C ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT-2 LCR[3]: TX and RX Parity Select Parity ...
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REV. 1.2.2 LCR[7]: Baud Rate Divisors Enable Baud rate generator divisor (DLL/DLM) enable. • Logic 0 = Data registers are selected (default). • Logic 1 = Divisor latch registers are selected. 4.7 Modem Control Register (MCR) - Read/Write The ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART 4.8 Line Status Register (LSR) - Read Only This register provides the status of data transfers between the UART and the host. If IER bit-2 is set to a logic 1, an ...
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REV. 1.2.2 MSR[0]: Delta CTS# Input Flag • Logic change on CTS# input (default). • Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt will ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART T 16: A RS485 H ABLE UTO ALF MSR[7] MSR[ 4.11 SCRATCH PAD REGISTER (SPR) - ...
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REV. 1.2 ABLE ELECTABLE FCTR B -3 FCTR ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART 4.13 Enhanced Feature Register (EFR) - Read/Write Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive character software flow control selection (see are selected, the ...
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REV. 1.2.2 EFR[5]: Special Character Detect Enable • Logic 0 = Special Character Detect Disabled (default). • Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with data in Xoff-2 register match ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART REGISTERS DLL DLM RHR THR IER FCR ISR LCR MCR LSR MSR SPR FCTR EFR TXCNT TXTRG RXCNT RXTRG XCHAR XON1 XON2 XOFF1 XOFF2 I/O SIGNALS TX[ch-3:0] IRTX[ch-3:0] RTS#[ch-3:0] DTR#[ch-3:0] T 19: ...
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REV. 1.2.2 ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation Thermal Resistance (10x10x1.4mm 64-LQFP) . ELECTRICAL CHARACTERIISTICS DC ELECTRICAL CHARACTERISTICS TA (-40 to +85 ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART F 16. XR16L784 VOL S IGURE INK 0.00 0.10 0.20 F 17. XR16L784 VOH S IGURE OURCE 16 ...
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REV. 1.2.2 AC ELECTRICAL CHARACTERISTICS TA (-40 + WHERE APPLICABLE S YMBOL TC1,TC2 Clock Pulse Period TOSC Oscillator Frequency TECK External Clock Frequency TAS Address Setup (16 Mode) TAH Address ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART F 18 IGURE ODE NTEL ATA A0-A7 Valid Address T AS CS# IOR# T RDV D0-D7 A0-A7 Valid Address T AS CS# IOW# D0- ...
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REV. 1.2 IGURE ODE OTOROLA A0-A7 T ADS CS# T RWS R/W# T RDA D0-D7 A0-A7 T ADS CS# T RWS R/W# T WDS D0-D7 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART F 20 IGURE ODEM NPUT UTPUT Active IOW# Change of RTS# State DTR# CD# CTS# DSR# INT IOR# RI IGURE ECEIVE NTERRUPT IMING RX ...
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REV. 1.2 IGURE RANSMIT NTERRUPT ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART PACKAGE DIMENSIONS, 64-LQFP A Seating Plane A Note: The control dimension is the millimeter column SYMBOL ...
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... Updated the 1.4mm-thick Quad Flat Pack package description from "TQFP" to "LQFP" consistent with the JEDEC and Industry norms. Clarified wake-up interrupt in Sleep Mode description. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART GENERAL DESCRIPTION ............................................................................................... 1 A ........................................................................................................................................... 1 PPLICATIONS F ................................................................................................................................................. 1 EATURES Figure 1. Block Diagram ....................................................................................................................... 1 Figure 2. Pin Out Assignment .............................................................................................................. 2 ............................................................................................................................ 2 ORDERING INFORMATION PIN DESCRIPTIONS ....................................................................................................... ...
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REV. 1.2.2 Figure 14. The Global Interrupt Registers, INT0, INT1, INT2 and INT3 ........................................... UART C [3:0] I ABLE HANNEL 3.1.2 General Purpose 16-bit Timer/Counter. [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (default 0xXX-XX-00-00) ............................................................................................................................. 22 Figure 15. Timer/Counter ...
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XR16L784 HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART Figure 23. Receive Interrupt Timing [FIFO Mode] ............................................................................ 47 Figure 24. Transmit Interrupt Timing [FIFO Mode] ........................................................................... 47 PACKAGE DIMENSIONS, 64-LQFP .............................................................................. .................................................................................................................................. 49 EVISION ISTORY TABLE OF CONTENTS ...