xr16v2652il32 Exar Corporation, xr16v2652il32 Datasheet - Page 9
xr16v2652il32
Manufacturer Part Number
xr16v2652il32
Description
High Performance Duart With 32-byte Fifo
Manufacturer
Exar Corporation
Datasheet
1.XR16V2652IL32.pdf
(48 pages)
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REV. 1.0.2
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 3 and 4
through
The V2652 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see
““Section 2.10, Programmable Baud Rate Generator with Fractional Divisor” on page
F
2.8
2.9
INTA/B Pin LOW = a byte in THR
INTA/B Pin LOW = a byte in THR
INTA/B Pin LOW = no data
IGURE
4. T
INTA and INTB Outputs
Crystal Oscillator or External Clock Input
22.
YPICAL
HIGH = THR empty
HIGH = transmitter empty
HIGH = 1 byte
summarize the operating behavior for the transmitter and receiver. Also see
C
RYSTAL
T
ABLE
T
ABLE
(FIFO D
(FIFO D
C
FCR B
FCR B
ONNECTIONS
3: INTA
4: INTA
IT
ISABLED
IT
ISABLED
-0 = 0
-0 = 0
AND
22-47pF
XTAL1
AND
C1
)
)
INTB P
INTB P
500K - 1M
INS
R2
22-47pF
XTAL2
IN
9
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
C2
O
Y1
O
PERATION FOR
PERATION
1.8432 MHz
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or FIFO empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or transmitter empty
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
(Optional)
24 MHz
0-120
R1
to
F
OR
FCR B
T
RANSMITTER
R
ECEIVER
IT
(FIFO E
-0 = 1 (FIFO E
FCR B
IT
NABLED
-0 = 1
10.”
NABLED
)
XR16V2652
Figures 17
)
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