xr16v2652il32 Exar Corporation, xr16v2652il32 Datasheet - Page 28
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xr16v2652il32
Manufacturer Part Number
xr16v2652il32
Description
High Performance Duart With 32-byte Fifo
Manufacturer
Exar Corporation
Datasheet
1.XR16V2652IL32.pdf
(48 pages)
XR16V2652
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See
•
•
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR bit-4 selects the even or odd parity format.
•
•
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
•
•
•
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR BIT-5 = logic 0, parity is not forced (default).
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced HIGH for the transmit and receive data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced LOW for the transmit and receive data.
Table 12
for parity selection summary below.
BIT-1
BIT-2
0
0
1
1
0
1
1
LENGTH
5,6,7,8
W
BIT-0
6,7,8
ORD
0
1
0
1
5
28
S
W
TOP BIT LENGTH
(B
5 (default)
1 (default)
ORD LENGTH
IT TIME
1-1/2
6
7
8
2
(
S
))
REV. 1.0.2