78p2343jat Teridian Semiconductor Corporation, 78p2343jat Datasheet - Page 22
![no-image](/images/no-image-200.jpg)
78p2343jat
Manufacturer Part Number
78p2343jat
Description
3-port E3/ds3/sts-1 With Jitter Attenuator
Manufacturer
Teridian Semiconductor Corporation
Datasheet
1.78P2343JAT.pdf
(37 pages)
- Current page: 22 of 37
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78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS
Note 1:
Page 22 of 37
TIMING DIAGRAM
PARAMETER
CKREF Duty Cycle
CKREF Frequency Stability
RCLK Duty Cycle
Data Propagation Delay
Receive Loss of Signal
Assert Timing
Receive Loss of Signal
De-assert Timing
RECEIVE TIMING CHARACTERISTICS:
RCLK
RCLKP=LOW
RNEG
RPOS
RECEIVE LINE
INPUT (REF)
(LINP,LINN)
RCLK
RCLKP=HIGH
At least a 100 S of software delay must be added after STS-1 LOS de-assertion to be compliant with
the ANSI T1.231 requirement of 100 to 250 S.
:
Receive Waveforms (E3/DS3/STS-1)
TRC/TRCF
SYMBOL
TPROP
2005 Teridian Semiconductor Corporation
TPROP
--
--
--
--
(continued)
TRCF
CONDITIONS
w.r.t. line-rate
frequency
E3 mode
DS3 mode
STS1 mode
E3 mode
DS3 mode
STS1 mode, see
Note 1
TRC
TPROP
MIN
-0.3
100
100
-20
2.3
2.3
40
40
10
10
NOM
140
150
130
130
3
3
MAX
+20
255
250
100
255
250
250
60
60
3
Rev 2.2
UNIT
ppm
ns
%
%
UI
UI
UI
UI
S
S
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