x4c105 Intersil Corporation, x4c105 Datasheet - Page 7

• Manufacturer Part Number: x4c105
• Description: Cpu Supervisor With Novram And Output Ports
• Manufacturer: Intersil Corporation

Acknowledge Polling
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
device initiates the internal non volatile write cycle.
Acknowledge polling can be initiated immediately. To
do this, the master issues a start condition followed by
the slave address byte for a write or read operation. If
the device is still busy with the high voltage cycle then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
Refer to the flow chart in Figure 8.
Figure 8. Acknowledge Polling Sequence
The disabling of the inputs during high voltage cycles
Command Sequence
command sequence?
Issue Slave Address
Byte (Read or Write)
Byte load completed
complete. Continue
High Voltage Cycle
Enter ACK Polling
by issuing STOP.
Continue Normal
Read or Write
Issue START
PROCEED
returned?
ACK
YES
YES
7
NO
NO
Issue STOP
Issue STOP
X4C105
Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the slave address byte is set to one. There are three
basic read operations: current address read, random
read, and sequential read.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power-up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.
Upon receipt of the slave address byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the data byte. The mas-
ter terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to Figure 9 for
the address, acknowledge, and data transfer sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Random Read
A random read operation allows the master to access
any memory location in the array. Prior to issuing the
slave address byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues
the word address byte. After acknowledging receipts
of the word address byte, the master immediately
issues another start condition and the slave address
byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 10 for the address,
acknowledge, and data transfer sequence.
March 18, 2005
FN8124.0