x4c105 Intersil Corporation, x4c105 Datasheet - Page 12

• Manufacturer Part Number: x4c105
• Description: Cpu Supervisor With Novram And Output Ports
• Manufacturer: Intersil Corporation

SERIAL AC SPECIFICATIONS T
Notes: (7) This parameter is periodically sampled and not 100% tested.
SERIAL TIMING DIAGRAMS
Bus Timing
t
t
SU: S1, S2,WP
HD: S1, S2,WP
SDA OUT
Symbol
t
t
t
t
t
SDA IN
HD:DAT
SU:STO
SU:STA
HD:STA
SU:DAT
t
(8) Cb = total capacitance of one bus line in pF.
t
f
t
HIGH
LOW
t
t
BUF
SCL
Cb
t
DH
t
AA
t
IN
SCL
R
F
t
SU:STA
SCL clock frequency
Pulse width of spikes to be suppressed by the input filter
SCL LOW to SDA data out valid
Time the bus must be free before a new transmission can start
Clock LOW time
Clock HIGH time
Start condition setup time
Start condition hold time
Data in setup time
Data in hold time
Stop condition setup time
Data output hold time
SDA and SCL rise time
SDA and SCL fall time
S1, S2, and WP setup time
S1, S2, and WP hold time
Capacitive load for each bus line
t
HD:STA
12
t
F
A
= -40°C to +85°C, V
t
SU:DAT
Parameter
t
HIGH
X4C105
t
LOW
CC
t
= +3.0V to +3.6V, unless otherwise specified.
HD:DAT
t
R
t
AA
t
DH
20 +.1Cb
20 +.1Cb
400kHz Option
Min.
100
0.1
1.3
1.3
0.6
0.6
0.6
0.6
0.4
0.4
50
0
0
0
t
(8)
(8)
BUF
t
Max.
SU:STO
400
300
300
400
0.9
50
March 18, 2005
Unit
kHz
ms
ms
pF
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
FN8124.0