x4c105 Intersil Corporation, x4c105 Datasheet
x4c105
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x4c105 Summary of contents
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... Logic 1 March 18, 2005 DESCRIPTION The low voltage X4C105 combines several functions into one device. The first is a 2-wire, 4Kbit serial EEPROM memory with write protection. A Write Pro- tect (WP) pin provides hardware protection for the upper half of this memory against inadvertent writes. ...
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... EEPROM only when power fails and the EEPROM is recalled to SRAM only on power-up. Output Ports The X4C105 has four output only ports. These are active whenever power is applied to the device. The state of the output pin reflects the value in the respec- tive SRAM bit. As such, these port pins provide a non- volatile state ...
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... The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data Figure 2. Valid Data Changes on the SDA Bus SCL SDA 3 X4C105 To Internal Voltage Supply V TRIP Start NOVRAM AUTOSTORE transfers, and provides the clock for both transmit and receive operations ...
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... Data Output from Receiver Start 4 X4C105 eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 4. The device will respond with an acknowledge after recognition of a start condition and if the correct device identifier and select bits are contained in the slave address byte ...
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... Figure 6. Writing 12 bytes to a 16-byte page starting at location 10. 7 Bytes Address = 6 5 X4C105 Page Write The device is capable of a page write operation initiated in the same manner as the byte write opera- tion; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes ...
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... SDA Bus Signals from the Slave 6 X4C105 Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write ...
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... Continue Normal Read or Write Command Sequence PROCEED 7 X4C105 Serial Read Operations Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the slave address byte is set to one. There are three basic read operations: current address read, random read, and sequential read ...
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... The device continues to output data for each acknowledge received. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. 8 X4C105 S Slave t a Address r ...
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... SDA line. Slave Byte Word Address The word address is either supplied by the master or obtained from an internal counter. The internal counter is undefined on a power-up condition. 9 X4C105 Data Data (1) (2) Write Protect Operations The WP pin provides write protection. The WP pin pro- tects the upper half of the array ...
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... V max. are for reference only and are not tested X4C105 COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those indicated in the operational sections of this specifi- cation) is not implied ...
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... SERIAL MEMORY AC CHARACTERISTICS Serial AC Test Conditions Input pulse levels V CC Input rise and fall times 10ns Input and output timing levels V CC Output load Standard output load 11 X4C105 = 3.0-3.6V CC Parameter Parameter Equivalent AC Output Load Circuit for 0.5 Max. Unit Test Conditions ...
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... Notes: (7) This parameter is periodically sampled and not 100% tested. ( total capacitance of one bus line in pF. SERIAL TIMING DIAGRAMS Bus Timing t F SCL t SU:STA t HD:STA SDA IN SDA OUT 12 X4C105 = -40°C to +85° +3.0V to +3.6V, unless otherwise specified Parameter t t HIGH LOW t SU:DAT t HD:DAT 400kHz Option Min ...
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... Bit of Last Byte NOVRAM AC CHARACTERISTICS NOVRAM AC Conditions of Test Input pulse levels V CC Input rise and fall times 10ns Input and output timing levels X4C105 Clk 1 Slave Address Byte t SU: S1,S2,WP ACK Stop Condition NOVRAM Equivalent A.C Load Circuits 0.5 Clk 9 ...
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... CL = 5pF, from the point when return high (whichever occurs first) to the time when the outputs are no longer driven. NOVRAM Read Cycle WES WE t D0-D3 14 X4C105 Parameter min; and t and t are periodically sampled and not 100% tested OHZ ...
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... LZ OLZ SOE HOE measured, with CL = 5pF, from the point when return high (whichever occurs first) to the time when the outputs are no longer driven. 15 X4C105 Parameter min; and t and t are periodically sampled and not 100% tested OHZ = 3.0V-3.6V -40°C to +85°C ...
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... NOVRAM WE Controlled Write Cycle D0-D3 (Data I/O) O0-O3 Previous Valid Data (Data Out) NOVRAM CE Controlled Write Cycle D0-D3 (Data In) O0-O3 (Data Out) 16 X4C105 t OES Data Valid t t OES Data Valid Previous Valid Data OEH t WPH ...
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... Output pins valid after V OVT V Reset valid V RVALID CC Low Voltage Detect and Output Pin Recall V TRIP PURST t R RST O0-O3 17 X4C105 Parameters Option 1)-default PURST = 2. 2. exceeds V CC TRIP t RPD t OVT Data Valid Min. Typ. ...
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... PACKAGING INFORMATION .0075 (.19) .0118 (.30) 0° - 8° See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 18 X4C105 20-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) .177 (4.5) .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .010 (.25) .019 (.50) .029 (.75) Detail A (20X) .252 (6.4) BSC .047 (1.20) Gage Plane Seating Plane ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 19 X4C105 X X –X ...