sx18ac ETC-unknow, sx18ac Datasheet
sx18ac
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sx18ac Summary of contents
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug 1.0 PRODUCT OVERVIEW 1.1 Introduction The Scenix SX family of configurable communications controllers are fabricated in an advanced CMOS process technology. The advanced process, combined with a RISC-based architecture, allows high-speed computa- tion, flexible I/O control, and efficient data manipulation. ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 1.0 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3.1 The Virtual Peripheral Concept . . . . . . . . 4 1.3.2 The Communications Controller . . . . . . . . 4 1.4 Programming and Debugging Support . . . . . . . . . . 4 1.5 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.0 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.0 Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Reading and Writing the Ports . . . . . . . . . . . . . . . . . 7 3.1.1 Read-Modify-Write Considerations . . . . . 9 3.2 Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2.1 MODE Register . . . . . . . . . . . . . . . . . . . . 9 3.2.2 Port Configuration Registers . . . . . . . . . . 9 3 ...
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... Key Features 50 MIPS Performance • SX18AC/SX20AC/SX28AC MHz operation SX18AC75/SX20AC75/SX28AC75 MHz • SX18AC/SX20AC/SX28AC instruction cycle internal interrupt response SX18AC75/SX20AC75/SX28AC75: 13.3 ns instruction cycle, 39.9 ns internal interrupt response • 1 instruction per clock (branches 3) EE/FLASH Program Memory and SRAM Data Memory • Access time of < provides single cycle access • ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 1.3 Architecture The SX devices use a modified Harvard architecture. This architecture uses two separate memories with sepa- rate address buses, one for the program and one for data, while allowing transfer of data from program mem- ory to SRAM. This ability allows accessing data tables from program memory ...
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... OSC2/Out O CMOS V P – dd Vss P – Note:I = input output, I/O = Input/Output Power, TTL = TTL input, CMOS = CMOS input Schmitt Trigger input, MIWU = Multi-Input Wakeup input © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 SX 28-PIN SX 20-PIN RTCC n. RA1 Vss ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 2.3 Part Numbering Device Pins I/O SX18AC/ SX18AC-I/ SX18AC75/ SX18AC/ SX18AC-I/ SX18AC75/ SX20AC/ SX20AC-I/ SX20AC75/ SX28AC/ SX28AC-I/ SX28AC75/ SX28AC/ SX28AC-I/ SX28AC75/ SX28AC/ SX28AC-I/ SX28AC75/ ...
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... To the CPU, the three ports are avail- able as the RA, RB, and RC file registers at data memory addresses 05h, 06h, and 07h, respectively. © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 The associated registers allow for each port bit to be indi- vidually configured under software control as shown below: ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 Output 1 = Hi-Z Input WR PLP_B or PLP_C 0 = Pullup Enable 1 = Pullup Disable LVL_B or LVL_C 0 = CMOS 1 = TTL WR ST_B or ST_C 0 = Schmitt Trigger Enable 1 = Schmitt Trigger Disable RD For example, suppose all four Port A pins are configured as outputs and with RA0 and RA1 to be high, and RA2 ...
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... Upon reset, the MODE register is initialized to 0Fh, which enables access to the port direction registers. © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 After a value is written to the MODE register, that setting remains in effect until it is changed by writing to the MODE register again. For example, you can write the ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 PLP_A, PLP_B, and PLP_C: Pullup Enable Registers (MODE=0Eh) Each register bit determines whether an internal pullup resistor is connected to the pin. Set the bit discon- nect the pullup resistor or clear the bit connect the pullup resistor. LVL_A, LVL_B, and LVL_C: Input Level Registers ...
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... Care should be exercised when writing to the STATUS register as the ALU status bits are updated upon completion of the write operation, possibly leaving © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 the STATUS register with a result that is different than intended. PA2 ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 4.3 OPTION Register RTE RTE RTW RTS PSA _IE _ES Bit 7 When the OPTIONX bit in the FUSE word is cleared, bits 7 and 6 of the OPTION register function as described below. When the OPTIONX bit is set, bits 7 and 6 of the OPTION register read as ‘1’s. ...
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... RC network - OSC2 is pulled high with a weak pullup (no CLKOUT output) Note: The frequencies are target values. © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 during normal device operation. Instead, the FUSE and FUSEX registers can only be accessed when the SX device is being programmed. The DEVICE register is a read-only, hard-wired register, programmed during the manufacturing process ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 5.2 FUSEX Word (Read/Program via Programming Command) IRCTRIM2 PINS IRCTRIM1 IRCTRIM0 Bit 11 IRCTRIM2: Internal RC oscillator trim bits. This 3-bit field adjusts the operation of the internal RC oscillator to make it operate within the target frequency range 4 MHz plus or minus 8%. Parts are shipped from the factory IRCTRIM0 untrimmed ...
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... The stack is physically and logically separate from data RAM. The program cannot read or write the stack. © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 6.2 Data Memory The data memory consists of 136 bytes of RAM, orga- nized as eight banks of 16 registers plus eight registers which are not banked ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 Function Registers INDF RTCC PC STATUS FSR © 2000 Scenix Semiconductor, Inc. All rights reserved. Bank 0 00 Registers (8 bytes) 07 SRAM (8 bytes) 0F Bank 4 Bank 3 Bank 2 30 Bank 1 10 Bank 0 SRAM (16 bytes each bank 128 bytes 3F total) 1F Figure 6-1. Data Memory Organization - 16 - Bank 0 is always accessed for ...
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... MODE MODE = © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 feature. The WKEN_B register (Wakeup Enable Regis- ter) allows any Port B pin or combination of pins to cause the wakeup. Clearing a bit in the WKEN_B register enables the wakeup on the corresponding Port B pin. If ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 7.2 Port B MIWU/Interrupt Configuration The WKPND_B register comes up with a random value upon reset. The user program must clear the register prior to enabling the wake-up condition or interrupts. The proper initialization sequence is: 1. Select the desired edge (through WKED_B register). 2. Clear the WKPND_B register. ...
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... Ext. Interrupt through Port B PD bit 0 = Power Down Mode, no Ext. Interrupt © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 edge to be either positive or negative. The WKEN_B and WKED_B registers are set to FFh upon reset. Setting a bit in the WKED_B register selects the falling edge while clearing the bit selects the rising edge on the correspond- ing Port B pin ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 All interrupts are global in nature; that is, no interrupt has priority over another. Interrupts are handled sequentially. Figure 8-2 shows the interrupt processing sequence. Once an interrupt is acknowledged, all subsequent global interrupts are disabled until return from servicing the cur- rent interrupt. The PC is pushed onto the single level ...
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... Table 9-1. External Component Selection for Crystal Oscillator(Vdd=5.0V) FOSC2:FOSC0 010 011 011 011 100 * 50 MHz fundamental crystal © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 Figure 9-1. Crystal Operation (or Ceramic Resonator) (HS OSC Configuration) Figure 9-2. External Clock Input Operation (HS OSC Configuration) Crystal C1 C2 Frequency ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 Table 9-2. External Component Selection for Murata Ceramic Resonators (Vdd=5.0V) Resonator FOSC2:FOSC0 Frequency 011 4 MHz 011 4 MHz 011 4 MHz 011 8 MHz 011 8 MHz 011 8 MHz 011 20 MHz 011 20 MHz 011 20 MHz 011 20 MHz 100 33 MHz 100 33 MHz 100 33 MHz 100 33 MHz ...
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... R C Figure 9-3. RC Oscillator Mode © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 9.3 Internal RC Mode The internal RC mode uses an internal oscillator, so the device does not need any external components MHz, the internal oscillator provides typically +/–8% accuracy over the allowed temperature range. The inter- ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 10.2 Watchdog Timer The watchdog logic consists of a Watchdog Timer which shares the same 8-bit programmable prescaler with the RTCC. The prescaler actually serves as a postscaler if used in conjunction with the WDT, in contrast to its use as a prescaler with the RTCC. 10.3 The Prescaler ...
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... RB2>RB1 ... © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 The final “mov” instruction in this example performs an exchange of data between the working register (W) and the CMP_B register. This exchange occurs only with Port B accesses. Otherwise, the “mov” instruction does not perform an exchange, but only moves data from the source to the destination ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 RB0 - RB1 + RB2 © 2000 Scenix Semiconductor, Inc. All rights reserved. Internal Data Bus CMP_B CMP_EN CMP_OE CMP_RES Figure 11-1. Comparator Block Diagram - MODE MODE = 08h 0 Point to CMP_B www.scenix.com ...
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... Note:Ripple counter is 10 bits for Power on Reset (POR) only. Figure 12-1. Block Diagram of On-Chip Reset Circuit © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 Figure 12-2 shows a power-up sequence where MCLR is not tied to the V and stabilize before MCLR pin is brought high. The device will actually come out of reset T MCLR goes high ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 Figure 12-3 shows the on-chip sequence where the MCLR and V together. The V signal is stable before the DRT time- dd out period expires. In this case, the device will receive a proper reset. However, Figure 12-4 depicts a situation where V rises too slowly. In this scenario, the DRT will ...
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... External reset during power down mode: 10 (TO, PD) External reset during Active mode: Unchanged (TO, PD) © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 A register that starts with an unknown value should be initialized by the software to a known value; you cannot simply test the initial state and rely on it starting in that state consistently ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 15.0 INSTRUCTION SET As mentioned earlier, the SX family of devices uses a modified Harvard architecture with memory-mapped input/output. The device also has a RISC type architec- ture in that there are 43 single-word basic instructions. The instruction set contains byte-oriented file register, bit- oriented file register, and literal/control instructions. ...
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... Bank 7 in FSR inc $1F ;increment file register ;1Fh in Bank 7 © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 15.6 Bit Manipulation The instruction set contains instructions to set, reset, and test individual bits in data memory. The device is capable of bit addressing anywhere in data memory. 15.7 Input/Output Operation The device contains three registers associated with each I/O port ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 15.10.2 Page Jump Operation When a JMP instruction is executed and the intended destination different page, the page select bits must be initialized with appropriate values to point to the desired page before the jump occurs. This can be done easily with SETB and CLRB instructions or by writing a value to the STATUS register ...
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... STACK 5 STACK 6 STACK 7 STACK 8 © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 15.12.2 Pop Operation When a return instruction is executed the subroutine stack is popped. Specifically, the contents of Stack 1 are copied into the program counter and the contents of each stack level are moved to the next higher level. For exam- ple, Stack 1 receives the contents of Stack 2, etc ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 15.13 Comparison and Conditional Branch Instructions The instruction set includes instructions such as DECSZ fr (decrement file register and skip if zero), INCSZ fr (increment file register and skip if zero), SNB bit (bit test file register and skip if bit clear), and SB bit (bit test file register and skip if bit set) ...
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... SWAP fr Swap High/Low Nibbles of fr (fr = <> fr) © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 cycles depends on the outcome of the instruction (such as the test-and-skip instructions) or the clocking mode (Compatible or Turbo). In those cases, all possible num- bers of cycles are shown in the table. ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 Mnemonic, Operands Bitwise Operations CLRB fr.bit Clear Bit in fr (fr.bit = 0) SB fr.bit Test Bit in fr and Skip if Set (test fr.bit and skip next instruction if bit is 1) SETB fr.bit Set Bit in fr (fr.bit = 1) SNB fr.bit Test Bit in fr and Skip if Clear (test fr.bit and skip ...
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... PAGE addr12 Load Page Number into STATUS(7:5) STATUS(7:5) = addr12(11:9) SLEEP Power Down Mode WDT = 00h stop oscillator ( clears prescaler if assigned) © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 Table 16-1. The SX Instruction Set (Continued) Description (Compatible Cycles Cycles Opcode ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 16.1 Equivalent Assembler Mnemonics Some assemblers support additional instruction mne- monics that are special cases of existing instructions or alternative mnemonics for standard ones. For example, an assembler might support the mnemonic “CLC” (clear Syntax CLC Clear Carry bit CLZ Clear Zero bit ...
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... Max. current into V pin dd Max. DC current into an input pin (with internal protection diode forward biased) Max. allowable sink current per I/O pin Max. allowable source current per I/O pin © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 ° ° - +85 C ° ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 17.2 DC Characteristics ° SX18/20/28AC (Temp Range Symbol Parameter Supply Voltage (Note rise rate S Vdd dd Supply Current, active I dd Supply Current, power down Input Levels MCLR, OSC1, RTCC Logic High Logic Low All Other Inputs V V CMOS ...
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... Clock in (OSC1) Low or High Time osL osH Clock in (OSC1) Rise or Fall Time osR osF Note:Data in the Typical (“TYP”) column is at 5V, 25 © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 ° Ta +70 C) and SX18/20/28AC-I (Temp Range: -40 Min Typ 0.032 1 ...
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... Output High Voltage V OSC2, Ports Port A Output Low Voltage V ol All Ports, OSC2 Note:Data in the Typical (“TYP”) column is at 5V, 25 © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 ° +70 C) Conditions MHz osc V = 5.0V MHz (Ext.) ...
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... Note:Data in the Typical (“TYP”) column is at 5V, 25 17.6 Comparator DC and AC Specifications Parameter Input Offset Voltage Input Common Mode Voltage Range Voltage Gain DC Supply Current (enabled) Response Time © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 ° +70 C) Min Typ DC ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 17.7 Typical Performance Characteristics (Room Temp) Active Supply Current Vs Operating Frequency (Crystal Clock Operating Frequency (MHz) © 2000 Scenix Semiconductor, Inc. All rights reserved. Active Supply Current Vs Operating Frequency ...
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... Active Supply Current Vs V (External Clock MHz 2.5 3.5 V © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 5.5 5.0 dd 4.5 5.5 ( Active Supply Current Vs V (Crystal Clock ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 17.7 Typical Performance Characteristics (continued) Active Supply Current Vs V (32 kHz External Clock) _ 600 _ 500 _ 400 _ 300 _ 200 _ 100 2 2 Port A/B/C Source Current © 2000 Scenix Semiconductor, Inc. All rights reserved. dd 160 120 4.5 5 5.5 (V) ...
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... SX18AC/DP SX18AC75/DP 0.008 - 0.012 (0.20 - 0.31) 0.430 max. (10.92 max.) o 0.300 BSC (7.62 BSC © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 DIMENSIONS ARE IN INCHES/(MILLIMETERS 0.050 BSC (1.27 BSC) 0.090 - 0.094 (2.29 - 2.39) 0.895 - 0.905 (22.73 - 22.99 0.015 min. (0.38 min.) 0.100 BSC (2.54 BSC) ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 SX20AC/SS SX20AC75/ 0.066 - 0.070 (1.68 - 1.78) 0.205 - 0.212 (5.20 - 5.38) © 2000 Scenix Semiconductor, Inc. All rights reserved 0.066 - 0.070 (1.68 - 1.78 0.039 (1.00) 1 0.039 (1.00) 0.205 - 0.212 (5.20 - 5.38) 20 0.010 - 0.015 (0.25 - 0.38) 0.0256 BSC (0.65 BSC) 0.278 - 0.289 0.002 - 0.008 (7.07 - 7.33) (0.05 - 0.21) www.scenix.com 0.301 - 0.311 (7.65 - 7.90) ...
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... SX28AC/SO SX28AC75/SO 0.090 - 0.094 (2.29 - 2.39) 0.292 - 0.299 (7.42 - 7.59) © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 14 15 0.050 BSC (1.27 BSC) 0.090 - 0.094 (2.29 - 2.39 0.035 - 0.045 (0.890 - 1.143) 1 0.045 - 0.055 (1.143 - 1.397) 0.292 - 0.299 7.42 - 7.59) 28 0.014 - 0.019 (0.35 - 0.48) 0.0050 - 0.0115 0.701 - 0.710 (0.127 - 0.292) (17.81 - 18.06) www.scenix.com 0.40 - 0.41 (10.16 - 10.41) ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 SX28AC/DP SX28AC75/DP 0.009 - 0.014 (0.23 - 0.36) 0.430 max. (10.92 max.) o 0.300 BSC (7.62 BSC © 2000 Scenix Semiconductor, Inc. All rights reserved. 1.360 - 1.370 (34.54 - 34.80 0.020 min. (0.51 min.) 0.100 BSC 0.045 - 0.055 (2.54 BSC) (1.14 - 1.40 0.280 - 0.295 (7.11 - 7.49) 28 0.130 nom. 0.180 max. (3.3 nom.) (4.57 max.) ...
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... SX28AC/SS SX28AC75/ 0.066 - 0.070 (1.68 - 1.78) 0.205 - 0.212 (5.20 - 5.38) © 2000 Scenix Semiconductor, Inc. All rights reserved. SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 14 15 0.0256 BSC (0.65 BSC) 0.066 - 0.070 (1.68 - 1.78) 0.397 - 0.407 (10.07 - 10.33 0.039 (1.00) 1 0.301 - 0.311 (7.65 - 7.90) 0.039 (1.00) 0.205 - 0.212 (5.20 - 5.38) 28 0.010 - 0.015 (0.25 - 0.38) 0.002 - 0.008 (0.05 - 0.21) www.scenix.com ...
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... SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75 Lit #: SXL-DS01-04 Sales and Tech Support Contact Information Sales and Tech Support Contact Information For the latest contact and support information on SX devices, please visit the Scenix Semiconductor website at For the latest contact and support information on SX devices, please visit the Scenix Semiconductor website at www ...