cop87l88rg National Semiconductor Corporation, cop87l88rg Datasheet - Page 25

• Manufacturer Part Number: cop87l88rg
• Description: 8-bit One-time Programmable Microcontroller With Kbytes Program Memory
• Manufacturer: National Semiconductor Corporation

WATCHDOG Operation
The WATCHDOG service window will restart when the
WDOUT pin goes high It is recommended that the user tie
the WDOUT pin back to V
pull WDOUT high
A WATCHDOG service while the WDOUT signal is active
will be ignored The state of the WDOUT pin is not guaran-
teed on reset but if it powers up low then the WATCHDOG
will time out and WDOUT will enter high impedance state
The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error The Clock Monitor error will continue
until the clock frequency has reached the minimum speci-
fied value after which the G1 output will enter the high im-
pedance TRI-STATE mode following 16 t
cles The Clock Monitor generates a continual Clock Moni-
tor error if the oscillator fails to start or fails to reach the
minimum specified frequency The specification for the
Clock Monitor is as follows
WATCHDOG AND CLOCK MONITOR SUMMARY
The following salient points regarding the WATCHDOG and
CLOCK MONITOR should be noted
1 t
1 t
Both the WATCHDOG and CLOCK MONITOR detector
circuits are inhibited during RESET
Following RESET the WATCHDOG and CLOCK MONI-
TOR are both enabled with the WATCHDOG having the
maximum service window selected
The WATCHDOG service window and CLOCK MONI-
TOR enable disable option can only be changed once
during the initial WATCHDOG service following RESET
The initial WATCHDOG service must match the key data
value in the WATCHDOG Service register WDSVR in or-
der to avoid a WATCHDOG error
Subsequent WATCHDOG services must match all three
data fields in WDSVR in order to avoid WATCHDOG er-
rors
The correct key data value cannot be read from the
WATCHDOG Service register WDSVR Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all 0’s
c l
c k
10 kHz No clock rejection
10 Hz Guaranteed clock rejection
CC
through a resistor in order to
(Continued)
c
–32 t
c
clock cy-
25
The WATCHDOG detector circuit is inhibited during both
the HALT and IDLE modes
The CLOCK MONITOR detector circuit is active during
both the HALT and IDLE modes Consequently the
COP888 inadvertently entering the HALT mode will be
detected as a CLOCK MONITOR error (provided that the
CLOCK MONITOR enable option has been selected by
the program)
With the single-pin R C oscillator mask option selected
and the CLKDLY bit reset the WATCHDOG service win-
dow will resume following HALT mode from where it left
off before entering the HALT mode
With the crystal oscillator mask option selected or with
the single-pin R C oscillator mask option selected and
the CLKDLY bit set the WATCHDOG service window will
be set to its selected value from WDSVR following HALT
Consequently the WATCHDOG should not be serviced
for at least 2048 instruction cycles following HALT but
must be serviced within the selected window to avoid a
WATCHDOG error
The IDLE timer T0 is not initialized with RESET
The user can sync in to the IDLE counter cycle with an
IDLE counter (T0) interrupt or by monitoring the T0PND
flag The T0PND flag is set whenever the thirteenth bit of
the IDLE counter toggles (every 4096 instruction cycles)
The user is responsible for resetting the T0PND flag
A hardware WATCHDOG service occurs just as the de-
vice
WATCHDOG should not be serviced for at least 2048
instruction cycles following IDLE but must be serviced
within the selected window to avoid a WATCHDOG error
Following RESET the initial WATCHDOG service (where
the service window and the CLOCK MONITOR enable
disable must be selected) may be programmed any-
where within the maximum service window (65 536 in-
struction cycles) initialized by RESET Note that this ini-
tial WATCHDOG service may be programmed within the
initial 2048 instruction cycles without causing a
WATCHDOG error
exits
the
IDLE
mode
Consequently
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