cop87l88rg National Semiconductor Corporation, cop87l88rg Datasheet - Page 17

• Manufacturer Part Number: cop87l88rg
• Description: 8-bit One-time Programmable Microcontroller With Kbytes Program Memory
• Manufacturer: National Semiconductor Corporation

UART
UART CONTROL AND STATUS REGISTERS
The operation of the UART is programmed through three
registers ENU ENUR and ENUI The function of the individ-
ual bits in these registers is as follows
ENU-UART Control and Status Register (Address at 0BA)
ENUR-UART Receive Control and Status Register
(Address at 0BB)
ENUI-UART Interrupt and Clock Source Register
(Address at 0BC)
0
1
R
RW Bit is read write
D
DESCRIPTION OF UART REGISTER BITS
ENU UART CONTROL AND STATUS REGISTER
TBMT This bit is set when the UART transfers a byte of
data from the TBUF register into the TSFT register for trans-
mission It is automatically reset when software writes into
the TBUF register
RBFL This bit is set when the UART has received a com-
plete character and has copied it into the RBUF register It
is automatically reset when software reads the character
from RBUF
ERR This bit is a global UART error flag which gets set if
any or a combination of the errors (DOE FE PE) occur
CHL1 CHL0 These bits select the character frame format
Parity is not included and is generated verified by hardware
CHL1
CHL1
CHL1
CHL1
XBIT9 PSEL0 Programs the ninth bit for transmission
when the UART is operating with nine data bits per frame
For seven or eight data bits per frame this bit in conjunction
with PSEL1 selects parity
PSEL1 PSEL0 Parity select bits
PSEL1
PSEL1
Bit is not used
STP2 STP78 ETDX SSEL XRCLK XTCLK
0RW
0RW
PEN
DOE
Bit 7
0RD
Bit7
Bit7
Bit is cleared on reset
Bit is set to one on reset
Bit is read-only it cannot be written by software
Bit is cleared on read when read by software as a one it is cleared
automatically Writing to the bit does not affect its state
e
e
e
e
e
e
PSEL1 XBIT9
0RW
0RW
0RD
0 CHL0
0 CHL0
1 CHL0
1 CHL0
FE
0 PSEL0
0 PSEL0
(Continued)
PSEL0
0RW
0RW
0RD
PE
e
e
e
e
e
e
0
1
0
1
SPARE RBIT9 ATTN XMTG RCVG
0
1
0RW
CHL1
0RW
0RW
The frame contains eight data bits
The frame contains seven data
bits
The frame contains nine data bits
Loopback Mode selected Trans-
mitter output internally looped
back to receiver input Nine bit
framing format is used
Odd Parity (if Parity enabled)
Odd Parity (if Parity enabled)
CHL0
0RW
0RW
0R
0RW
ERR
0RW
0R
RBFL TBMT
0RW
ERI
0R
0R
0RW
Bit0
Bit0
ETI
1R
0R
Bit 0
17
PSEL1
PSEL1
PEN This bit enables disables Parity (7- and 8-bit modes
only)
PEN
PEN
ENUR UART RECEIVE CONTROL AND
STATUS REGISTER
RCVG This bit is set high whenever a framing error occurs
and goes low when RDX goes high
XMTG This bit is set to indicate that the UART is transmit-
ting It gets reset at the end of the last frame (end of last
Stop bit)
ATTN ATTENTION Mode is enabled while this bit is set
This bit is cleared automatically on receiving a character
with data bit nine set
RBIT9 Contains the ninth data bit received when the UART
is operating with nine data bits per frame
SPARE Reserved for future use
PE Flags a Parity Error
PE
PE
FE Flags a Framing Error
FE
FE
DOE Flags a Data Overrun Error
DOE
DOE
ENUI UART INTERRUPT AND
CLOCK SOURCE REGISTER
ETI This bit enables disables interrupt from the transmitter
section
ETI
ETI
ERI This bit enables disables interrupt from the receiver
section
ERI
ERI
XTCLK This bit selects the clock source for the transmitter
section
XTCLK
XTCLK
XRCLK This bit selects the clock source for the receiver
section
XRCLK
XRCLK
SSEL UART mode select
SSEL
SSEL
e
e
e
e
e
e
e
e
e
e
e
e
0
1
0
1
e
e
0
1
0
1
e
e
e
e
0
1
e
e
0
1
0
1
1 PSEL0
1 PSEL1
Indicates no Framing Error has been detected
since the last time the ENUR register was read
Indicates the occurrence of a Framing Error
Indicates no Parity Error has been detected since
the last time the ENUR register was read
Indicates the occurrence of a Parity Error
0
1
0
1
Interrupt from the transmitter is disabled
Interrupt from the transmitter is enabled
Interrupt from the receiver is disabled
Interrupt from the receiver is enabled
Parity disabled
Parity enabled
Indicates no Data Overrun Error has been de-
tected since the last time the ENUR register
was read
Indicates the occurrence of a Data Overrun Er-
ror
Asynchronous Mode
Synchronous Mode
The clock source is selected through the
PSR and BAUD registers
Signal on CKX (L1) pin is used as the clock
The clock source is selected through the
PSR and BAUD registers
Signal on CKX (L1) pin is used as the clock
e
e
0
1
Mark(1) (if Parity enabled)
Space(0) (if Parity enabled)
http
www national com