cop87l88rg National Semiconductor Corporation, cop87l88rg Datasheet - Page 22

• Manufacturer Part Number: cop87l88rg
• Description: 8-bit One-time Programmable Microcontroller With Kbytes Program Memory
• Manufacturer: National Semiconductor Corporation

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Comparators
CMPSL REGISTER (ADDRESS X’00B7)
The CMPSL register contains the following bits
CMP1EN Enable comparator 1
CMP1RD Comparator 1 result (this is a read only bit which
CMP10E
CMP2EN Enable comparator 2
CMP2RD Comparator 2 result (this is a read only bit which
CMP20E
Note that the two unused bits of CMPSL may be used as
software flags
Comparator outputs have the same spec as Ports L and G
except that the rise and fall times are symmetrical
Unused CMP20E CMP2RD CMP2EN CMP10E CMP1RD CMP1EN Unused
Bit 7
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will read as 0 if the comparator is not enabled)
Selects pin I3 as comparator 1 output provided
that CMPIEN is set to enable the comparator
will read as 0 if the comparator is not enabled)
Selects pin I6 as comparator 2 output provided
that CMP2EN is set to enable the comparator
y is VIS page y
Arbitration
(1) Highest
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16) Lowest
(Continued)
Ranking
i
0
Software
Reserved
External
Timer T0
Timer T1
Timer T1
MICROWIRE PLUS
Reserved
UART
UART
Timer T2
Timer T2
Timer T3
Timer T3
Port L Wake Up
Default
Source
Bit 0
22
INTR Instruction
for Future Use
Pin G0 Edge
Underflow
T1A Underflow
T1B
BUSY Goes Low
for Future Use
Receive
Transmit
T2A Underflow
T2B
T3A Underflow
T3B
Port L Edge
VIS Instr Execution
without Any Interrupts
Interrupts
The devices support a vectored interrupt scheme It sup-
ports a total of fourteen interrupt sources The following ta-
ble lists all the possible device interrupt sources their arbi-
tration ranking and the memory locations reserved for the
interrupt vector for each source
Two bytes of program memory space are reserved for each
interrupt source All interrupt sources except the software
interrupt are maskable Each of the maskable interrupts
have an Enable bit and a Pending bit A maskable interrupt
is active if its associated enable and pending bits are set If
GIE
be interrupted as soon as it is ready to start executing an
instruction except if the above conditions happen during the
Software Trap service routine This exception is described
in the Software Trap sub-section
The interruption process is accomplished with the INTR in-
struction (opcode 00) which is jammed inside the Instruc-
tion Register and replaces the opcode about to be execut-
ed The following steps are performed for every interrupt
1 The GIE (Global Interrupt Enable) bit is reset
2 The address of the instruction about to be executed is
3 The PC (Program Counter) branches to address 00FF
Description
pushed into the stack
This procedure takes 7 t
e
1 and an interrupt is active then the processor will
Hi-Low Byte
0yFE– 0yFF
0yFC– 0yFD
0yFA– 0yFB
0yF8– 0yF9
0yF6– 0yF7
0yF4– 0yF5
0yF2– 0yF3
0yF0 – 0yF1
0yEE – 0yEF
0yEC– 0yED
0yEA– 0yEB
0yE8 – 0yE9
0yE6– 0yE7
0yE4 – 0yE5
0yE2– 0yE3
0yE0– 0yE1
Address
c
Vector
cycles to execute