mc908jl16 Freescale Semiconductor, Inc, mc908jl16 Datasheet - Page 136

no-image

mc908jl16

Manufacturer Part Number
mc908jl16
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mc908jl16CDWE
Manufacturer:
Freescale
Quantity:
2 865
Part Number:
mc908jl16CDWE
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
mc908jl16CFA
Manufacturer:
JAE
Quantity:
332
Part Number:
mc908jl16CFJE
Manufacturer:
Freescale Semiconductor
Quantity:
1 806
Part Number:
mc908jl16CFJE
Manufacturer:
FREESCALE
Quantity:
2 654
Part Number:
mc908jl16CFJE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc908jl16CFJE
Manufacturer:
FREESCALE
Quantity:
2 654
Part Number:
mc908jl16CFJE
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
mc908jl16CFJER
Manufacturer:
Freescale Semiconductor
Quantity:
29 890
Part Number:
mc908jl16CFJER
Manufacturer:
Freescale
Quantity:
198
Part Number:
mc908jl16CFJER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc908jl16CPE
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
mc908jl16CSPE
Manufacturer:
FREESCALE
Quantity:
20 000
Analog-to-Digital Converter (ADC)
ADLSMP — Long Sample Time Configuration
ACLKEN — Asynchronous Clock Source Enable
136
This bit configures the sample time of the ADC10 to either 3.5 or 23.5 ADCK clock cycles. This adjusts
the sample period to allow higher impedance inputs to be accurately sampled or to maximize
conversion speed for lower impedance inputs. Longer sample times can also be used to lower overall
power consumption in continuous conversion mode if high conversion rates are not required.
This bit enables the asynchronous clock source as the input clock to generate the internal clock ADCK,
and allows operation in stop mode. The asynchronous clock source will operate between 1 MHz and
2 MHz if the ADLPC bit is clear, and between 0.5 MHz and 1 MHz if the ADLPC bit is set. As long as
the internal clock ADCK, which is equal to the selected input clock divided by ADIV, is at a frequency
(f
operation is guaranteed.
ADCK
1 = Long sample time (23.5 cycles)
0 = Short sample time (3.5 cycles)
1 = The asynchronous clock is selected as the input clock source (the clock generator is only
0 = The ADICLK bit specifies the input clock source and conversions will not continue in stop mode
) between the minimum and maximum required clock frequencies (considering ALPC), correct
enabled during the conversion)
MC68HC908JL16 Data Sheet, Rev. 1.1
Freescale Semiconductor

Related parts for mc908jl16