mc9s08ac128 Freescale Semiconductor, Inc, mc9s08ac128 Datasheet - Page 14

• Manufacturer Part Number: mc9s08ac128
• Description: 8-bit Hcs08 Central Processor Unit Cpu
• Manufacturer: Freescale Semiconductor, Inc

Chapter 3 Electrical Characteristics and Timing Specifications
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P
for a known T
value of T
3.5
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits and
JEDEC Standard for Non-Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed
for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
3.6
This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various
operating modes.
14
Num C
1
2
3
4
Human Body
Machine
Latch-up
A
.
ESD Protection and Latch-Up Immunity
DC Characteristics
A
Model
C Human Body Model (HBM)
C Machine Model (MM)
C Charge Device Model (CDM)
C Latch-up Current at T
. Using this value of K, the values of P
Series Resistance
Storage Capacitance
Number of Pulse per pin
Series Resistance
Storage Capacitance
Number of Pulse per pin
Minimum input voltage limit
Maximum input voltage limit
Table 3-5. ESD and Latch-Up Protection Characteristics
Table 3-4. ESD and Latch-up Test Conditions
K = P
A
Rating
= 125°C
MC9S08AC128 Series Data Sheet, Rev. 1
D
× (T
Description
Preliminary — Subject to Change
A
+ 273°C) + θ
D
and T
J
can be obtained by solving equations 1 and 2 iteratively for any
JA
× (P
Symbol
V
V
V
I
D
HBM
CDM
LAT
MM
)
2
Symbol
R1
R1
C
C
–
–
± 2000
± 200
± 500
± 100
Min
Value
1500
– 2.5
100
200
7.5
3
0
3
Freescale Semiconductor
Max
–
–
–
–
D
(at equilibrium)
Unit
pF
pF
Ω
Ω
V
V
Unit
mA
V
V
V
Eqn. 3-3