str755fvx STMicroelectronics, str755fvx Datasheet - Page 46
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str755fvx
Manufacturer Part Number
str755fvx
Description
Arm7tdmi-s, 32-bit Mcu With Flash, Smi, 3 Std 16-bit Timers Pwm Timer, Fast 10-bit Adc, I2c, Uart, Ssp, Usb And Can
Manufacturer
STMicroelectronics
Datasheet
1.STR755FVX.pdf
(73 pages)
Electrical parameters
Table 22.
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R
2. t
46/71
f
R
C
C
i
t
2
OSC32K
SU(OSC32K)
F
L1
L2
Refer to crystal/ceramic resonator manufacturer for more details
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal/ceramic
resonator manufacturer
Symbol
SU(OSC32K)
(2)
OSC32K crystal / ceramic resonator oscillator
The STR7 RTC clock can be supplied with a 32.768 kHz Crystal/Ceramic resonator
oscillator. All the information given in this paragraph are based on product characterisation
with specified typical external components. In the application, the resonator and the load
capacitors have to be placed as close as possible to the oscillator pins in order to minimize
output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, package, accuracy...).
OSC32K crystal / ceramic resonator oscillator
Figure 22. Typical application with a 32.768 kHz crystal or ceramic resonator
PLL Characteristics
PLL Jitter Terminology
G
G
is the start-up time measured from the moment it is enabled (by software) to a stabilized 32 kHz oscillation is
Oscillator Frequency
Feedback resistor
Recommended load capacitance
versus equivalent serial resistance of
the crystal or ceramic resonator (R
XT2 driving current
startup time
Self-referred single period jitter (period jitter)
Period Jitter is defined as the difference of the maximum period (T
period (T
between 2 consecutive clock rising edges and T
between 2 consecutive clock rising edges.
See
Self-referred long term jitter (N period jitter)
Self-referred long term Jitter is defined as the difference of the maximum period (T
and minimum period (T
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
Figure 23
min
Parameter
) at the output of the PLL where T
C
L2
C
L1
min
) at the output of the PLL where T
S
32 kHz
RESONATOR
)
(1)
V
V
R
V
V
V
DD_IO
DD_IO
DD_IO
IN
S
DD_IO
=TBD
=V
SS
XRTC1
XRTC2
=3.3 V
=5.0 V
=3.3 V or 5.0 V
Conditions
is stabilized
max
R
min
F
is the maximum time difference
i
2
is the minimum time difference
FEEDBACK
max
LOOP
TBD
TBD
Min
270
160
is the maximum time
max
32.768
TBD
STR750
Typ
310
2.5
) and minimum
f
OSC32K
S
Max
TBD
TBD
370
250
value.
STR750F
Unit
max
kHz
kΩ
pF
µA
s
)